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HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS81C4x60
User's Manual (Ver. 1.1)
Version 1.1 Published by MCU Application Team Heung-il Bae(hibae@hynix.com), Byoung-jin Lim( bjinlim@hynix.com) (c)2001 Hynix Semiconductor Inc. All rights reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS81C4x60
HMS81C4x60
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
1. OVERVIEW
1.1 Description
The HMS81C4x60 is an advanced CMOS 8-bit microcontroller with 60K bytes of ROM. This is one of the HMS800 family. This is a powerful microcontroller which provides a high flexibility and cost effective solution to many TV applications. The HMS81C4x60 provides following standard features: 60K bytes of ROM, 1024 bytes of RAM, 8/16-bit timer/counter, onchip PLL oscillator and clock circuitry. In addition, there are other package types, HMS81C4360(32PDIP), HMS81C4360SK(32SKDIP), HMS81C4460(42SDIP). This document is explained for the base of HMS81C4x60, the eliminated functions are same as below.
Device name HMS81C4260 HMS87C4260 ROM Size 60K bytes EPROM Size 60K bytes RAM Size 1024bytes 1024bytes I/O 31 31 Package 52SDIP 52SDIP
1.2 Features
* 60K Bytes of On-chip Program Memory * 1024 Bytes of On-chip Data RAM * Minimum Instruction Cycle Time - 256ns (NOP operation) * PLL Oscillator for OSD and System Clock - External 4MHz Crystal Input * 31 Programmable I/O pins - 26 Input/Output and 5 Input pins * I2C Bus Interface - Multimaster (2 Pairs interface pins) * A/D Converter - 8-bit x 5 ch * Pulse Width Modulation - 14-bit x 1 ch - 8-bit x 5 ch * Timer - Timer/Counter : 8-bit x 4 ch(16-bit x 2 ch) - Basic interval timer - Watch Dog Timer * Number of Interrupt Source - 16 Interrupts - 3 External Interrupts * On Screen Display - 512 character fonts pattern - Character Size : 1.0, 1.5, 2.0 times - Character Pixel size : 12 x 10, 12 x 12, 12 x 14, 12 x 16, 16 x 18 - Display Capability : 48 Characters x 16 Lines - Character, Background color : 512 colors, 8 pallet - Special functions : Rounding, Outline, Shadow, Underline, Double scanned line OSD * Buzzer Driving Port - 500Hz ~ 250KHz @4MHz (Duty 50%) * Vertical Blanking Interveral Information capture for EIA-608(Closed Caption) or VPS, etc
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HMS81C4x60
1.3 Development Tools
Note: There are several setting switches in the Emulator. User should read carefully and do setting properly before developing the program. Otherwise, the Emulator may not work properly.
The HMS87C4x60 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and EPROM programmers. There are two different type programmers such as single type and gang type. For more detail, refer to EPROM Programming chapter. Macro assembler operates under the MSWindows 95/98TM. Please contact sales part of Hynix Semiconductor.
1.4 Ordering Information
Device name Mask ROM version OTP ROM version Mask ROM version OTP ROM version Mask ROM version OTP ROM version Mask ROM version OTP ROM version HMS81C4260 HMS87C4260 HMS81C4360SK HMS87C4360SK HMS81C4360 HMS87C4360 HMS81C4460 HMS87C4460 ROM Size (bytes) 60K bytes 60K bytes EPROM (OTP) 60K bytes 60K bytes EPROM (OTP) 60K bytes 60K bytes EPROM (OTP) 60K bytes 60K bytes EPROM (OTP) RAM size 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes Package 52SDIP 52SDIP 32SKDIP 32SKDIP 32PDIP 32PDIP 42SDIP 42SDIP
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2. BLOCK DIAGRAM
RESET
TEST
Xin Xout
Vdd
YM YS R G B
PLL OSD CLOCK GENERATION / SYSTEM CONTROLLER G8MC CORE
CVBS SCAP
D ATA
SLICER
Vss
VS
HS
RAM ( 1024)
R10/AN0 R11/AN1 R12/AN2 R13/AN3 R14/AN4
PRESCALER /BIT ADC WATCH DOG TIMER
MASK ROM ( User ROM : 60KB Font ROM : 32KB )
R30/PWM0 R31/PWM1 R32/PWM2 R33/PWM3 R34/PW M 4 R35/PW M 5
PWM
BUZZER R4 PORT REMOCON R3 PORT R2 PORT INTERRUPT CONTROLLER R1 PORT R0 PORT
R40 ~ R43
R36/BUZ
R40/SCL0 R41/SDA0
R30 ~ R37
R42/S CL1 R43/SDA1
I2C
R20 ~ R25
R10 ~ R14
R24/EC2 R25/EC3 R37/TM R1
R00 ~ R07
TIMER
R21/INT1
R22/INT2
Figure 2-1 Block Diagram
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R23/INT3
3
HMS81C4x60
3. PIN ASSIGNMENT
R40/SCL0 R41/SDA0 R42/SCL1 R43/SDA1 R04 R05 R06 R07 VDD R14/AD4 SCAP CVBS VDD VSS R10/AD0 R11/AD1 R12/AD2 R13/AD3 HS VS R20 R21/INT1 R22/INT2 R23/INT3 R24/EC2 R25/EC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44
R30/PWM0 R31/PWM1 R32/PWM2 R33/PWM3 R34/PWM4 R35/PWM5 R36/BUZ R37/TMR1 TEST VSS YM YS B G R VDD VSS XIN XOUT RESET R03 R02 VDD VSS R01 R00
HMS81C4260
52SDIP
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Figure 3-1 52SDIP
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R40/SCL0 R41/SDA0 R42/SCL1 R43/SDA1 R04 VDD R14/AD4 SCAP CVBS VDD VSS R10/AD0 R11/AD1 R12/AD2 R13/AD3 HS VS R21/INT1 R22/INT2 R23/INT3 R24/EC2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34
R31/PWM1 R32/PWM2 R33/PWM3 R34PWM4 R35/PWM5 R36/BUZ R37/TMR1 TEST YM YS B G R XIN XOUT RESET R03 R02 R01 R00 R25/EC3
HMS81C4460
42SDIP
33 32 31 30 29 28 27 26 25 24 23 22
Figure 3-2 42SDIP
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HMS81C4x60
R40/SCL0 R41/SDA0 R42/SCL1 R43/SDA1 VDD R14/AD4 SCAP CVBS VDD VSS R10/AD0 R13/AD3 HS VS R21/INT1 R22/INT2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
R33/PWM3 R34/PWM4 R35/PWM5 R37/TMR1 TEST YM YS B G R XIN XOUT RESET R02 R24/EC2 R23/INT3
HMS81C4360SK
32SKDIP
25 24 23 22 21 20 19 18 17
Figure 3-3 32SKDIP
R40/SCL0 R41/SDA0 R42/SCL1 R43/SDA1 VDD R14/AD4 SCAP CVBS VDD VSS R10/AD0 R11/AD1 R12/AD2 R13/AD3 HS VS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
R34PWM4 R35PWM5 R37/TMR1 TEST YM YS B G R XIN XOUT RESET R02 R24/EC2 R23/INT3 R21/INT1
HMS81C4360
32PDIP
25 24 23 22 21 20 19 18 17
Figure 3-4 32PDIP
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4. PACKAGE DIAGRAM
52 27
0 ~ 15
13.97
15.24
HYNIX HMS81C4260
1 26
0.25
0.25 0.25 0.05
45.97
0.13
3.81
4.38 Max.
0.76
0.13
0.13 0.50 Min.
UNIT: mm
3.24 0.47 0.13 1.02 0.25 1.778 0.25 0.20
32
17
HYNIX HMS81C4360
1 16
UNIT: inch
TYP 0.600 BSC 0.550 0.530
1.665 1.645 0.2 max
MIN 0.015 0.140 0.120 0.022 0.015 0 ~ 15
2 0.01 8 0.00
0.065 0.045
0.1 BSC
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HMS81C4x60
42
22
0 ~ 15
13.97
15.24
HYNIX HMS81C4460
1 21
0.25
0.25 0.25 0.05
36.83
0.13
3.81
4.38 Max.
0.76
0.13
0.13 0.50 Min.
UNIT: mm
3.24 0.47 0.13 1.02 0.25 1.778 0.25 0.20
32
17 10.16 8.89
0 ~ 15
HYNIX HMS81C4360SK
1 16
0.25
0.25 0.25 0.05
27.68
0.13
3.81
4.38 Max.
0.76
0.13
0.13 0.50 Min.
UNIT: mm
3.24 0.47 0.13 1.02 0.25 1.778 0.25 0.20
Figure 4-1 Package Diagram
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should not be connected . RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R14: R1 is a 5-bit read only port. R1 pins 1 or 0 written to the Port Direction Register can be used as inputs. In addition, R1 serves the functions of the various following special features.
Port pin R10 R11 R12 R13 R14 Alternate function AD0 (A/D converter input 0) AD1 (A/D converter input 1) AD2 (A/D converter input 2) AD3 (A/D converter input 3) AD4 (A/D converter input 4) Port pin R30 R31 R32 R33 R34 R35 R36 R37 Alternate function PWM0 (Pulse Width Modulation output 0) PWM1 (Pulse Width Modulation output 1) PWM2 (Pulse Width Modulation output 2) PWM3 (Pulse Width Modulation output 3) PWM4 (Pulse Width Modulation output 4) PWM5 (Pulse Width Modulation output 5) with 14bit resolution BUZ (Buzzer output) TMR1 (Timer Interrupt 1)
R30~R37: R3 is 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R3 serves the functions of the various following special features.
R40~R43: R4 is a 4-bit open drain I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. In addition, R4 serves the functions of the various following special features.
Port pin R40 R41 R42 R43 Alternate function SCL0 (I2C Clock 0) SDA0 (I2C Data0) SCL1 (I2C Clock 1) SDA1 (I2C Data 1)
R20~R25: R2 is a 6-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. In addition, R2 serves the functions of the various following special features.
Port pin R21 R22 R23 R24 R25 Alternate function INT1 (External interrupt input 1) INT2 (External interrupt input 2) INT3 (External interrupt input 3) EC2 (Event counter input 2) EC3 (Event counter input 3)
R,G,B: R,G,B are output port. Each pins controls Red, Green, Blue color control. YM,YS: YM,YS are CMOS output port. Each pins controls Background, Edge control. HS,VS: HS,VS are CMOS input port. Each pins Vertical Sync. input and Horizaltal Sync. inputs. CVBS: CVBS is a CVBS(Composit Video in) signal input pin.
PIN NAME VDD VSS
Pin No. 9,13,30, 37 14,29, 36,43
In/Out Supply voltage Circuit ground Table 5-1 Port Function Description
Function
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HMS81C4x60
PIN NAME TEST RESET XIN XOUT HS VS R G B YS YM R30/PWM0 R31/PWM1 R32/PWM2 R33/PWM3 R34/PWM4 R35/PWM5 R36/BUZ R37/TMR1 R40/SCL0 R41/SDA0 R42/SCL1 R43/SDA1 R20 R21/INT1 R22/INT2 R23/INT3 R24/EC2 R25/EC3 SCAP R10/AD0 R11/AD1 R12/AD2 R13/AD3 R14/AD4 CVBS
Pin No. 44 33 35 34 19 20 38 39 40 41 42 52 51 50 49 48 47 46 45 1 2 3 4 21 22 23 24 25 26 11 15 16 17 18 10 12
In/Out I I I O I I O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I Table 5-1 Port Function Description A/D conversion functions External interrupt functions I2C functions (open drain) PWM functions
Function TEST signal input (internal pull up resister) Reset signal input Main oscillation input Main oscillation output Horisontal Sync. input Vertical Sync. input Red signal output Green signal output Blue signal output Edge signal output Background signal output 8bit PWM (pull up) 8bit PWM (pull up) 8bit PWM (pull up) 8bit PWM (pull up) 8bit PWM 14bit PWM Buzzer (pull up) Timer Interrupt 1 I2C Serial clock 0 I2C Serial data 0 I2C Serial clock 1 I2C Serial data 1 (pull up) External interrupt input 1 External interrupt input 2 (pull up) External interrupt input 3 Event counter input 2 Event counter input 3 (pull up) Data slicer comparation reference voltage Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Composit video input
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HMS81C4x60
PIN NAME R00 R01 R02 R03 R04 R05 R06 R07
Pin No. 27 28 31 32 5 6 7 8
In/Out I/O I/O I/O I/O I/O I/O I/O I/O Table 5-1 Port Function Description Digital I/O functions
Function (normal I/O, pull up) (normal I/O, pull up) (normal I/O) (normal I/O, pull up) (open drain, pull up) (open drain, pull up) (open drain, pull up) (open drain, pull up)
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HMS81C4x60
6. PORT STRUCTURES
XIN, XOUT R14~10, CVBS
VDD VDD I Data out XIN VDD VSS VSS XOUT STOP VSS Main frequency clock Analog in Analog in VSS VSS Data in Data in Schmitt Out Enable VSS Pin
VDD
VDD
U{
R03~R00,R37~R30,HS,VS,YS,YM
VDD VDD I/O Data out Out Enable VSS Data in Schmitt Pin Data out Out Enable VSS VSS
R07~R04, R43~R40, TEST
VDD I/O Pin
VSS Data in Data in
U{
Data in Schmitt
U{
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November 2001 Ver 1.1
HMS81C4x60
R,G,B
VDD
SCAP
VDD I/O Data In Pin
VSS VDD I/O Pin
VSS
VSS
R25~R20, RESET
VDD VDD I/O Data out Out Enable VSS Pin
VSS Data in Data in Schmitt
U{
Noise Filter
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13
HMS81C4x60
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of Vss pin.........................160 mA Maximum current into VDD pin ..........................160 mA Maximum current sunk by(IOL per I/O Pin) .........20 mA Maximum output current sourced by (IOH per I/O Pin) .................................................................................8 mA Maximum current (IOL) .................................... 100 mA Maximum current (IOH)...................................... 80 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition Min. VDD=4.5~5.5V fXIN=4MHz 4.5 -10 Max. 5.5 4.0(typical) 70 V MHz C Unit
7.3 DC Electrical Characteristics
(TA=-10~70C, VDD=4.5~5.5V),
Specifications Parameter Symbol VIH VIL VOH VOL IDD Condition Min. High level input voltage Low level input voltage High level output voltage Low level output voltage Supply current in ACTIVE mode TEST, RESET, Xin, R0, R1, R2, R3, HS, VS TEST, RESET, Xin, R0, R1, R2, R3,R4 HS, VS IOH = -5mA R0, R1, R2, R3, YS, YM IOL = 5mA R0, R1, R2, R4 VDD VDD = 5.5v, VPIN = 0.4V TEST, R00, R01, R03, R04, R05, R06, R07, R20, R22, R25, R30, R31, R32, R33 R36 VDD = 5.5V, VPIN = VDD All input, I/O pins except XIN 0.8 VDD 0 VDD - 1
-
Unit Typ. 40 Max. VDD 0.12 VDD 1.0 80 V V V v mA
-
pull-up lekage current
IRUP
-1.5
-400
A
High input leakage current
IIZH
-5
-
5
A
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November 2001 Ver 1.1
HMS81C4x60
Specifications Parameter Low input leakage current RAM data retention voltage Hysterisis Comparator operating range Comparator resolution RGB DAC Resolution 1 Symbol Condition Min. IIZL VRAM Vt+ ~ VtVrCVBS VaCVBS RGBR1 VDD = 5.5V, VPIN = 0V All input, I/O pins except XIN, OSC1 VDD TEST, RESET, Xin, HS, VS, R07 ~ R00, R21, R23, R24, R25, R37 ~ R30 VDD = 5V CVBS pin VDD = 5V CVBS pin VDD = 5V No in/out current in R,G,B pin RGB DAC On No in/out current in R,G,B pin Level 0 Level 1 RGB DAC Output voltage Level 2 VRGB Level 3 Level 4 Level 5 Level 6 Level 7 VDD = 5V RGB DAC On Level 7 IOH = -3mA VDD = 5V RGB DAC On Level 0 IOL = 3mA 3/40Vdd 5/40Vdd 8/40Vdd 12/40Vdd 17/40Vdd 23/40Vdd 30/40Vdd 38/40Vdd V -5 1.2 1.0 1.2 Typ. Max. 5 3.5 0.08 5 A V V V V % Unit
RGB Voh
Vohrgb
3.1
3.5
3.9
V
RGB Vol
Volrgb
0.4
0.6
0.8
V
7.4 AC Characteristics
(TA=-10~70C, VDD=5V10%, VSS=0V)
Specifications Parameter Crystal oscillator Frequency External Clock Pulse Width Symbol fXIN tMCPW tSCPW tMRCP,tMFCP tSRCP,tSFCP Pins Min. XIN XIN SCLK XIN SCLK 3 180 0.5 Typ. 4 20 20 Max. 5 350 MHz nS S nS nS Unit
External Clock Transition Time
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HMS81C4x60
Specifications Parameter Oscillation Stabilizing Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width Event Counter Transition Time Symbol tST tIW tRST tECW tREC,tFEC Pins Min. XIN, XOUT INT1~3 RESET EC2, EC3 EC2, EC3 2 8 2 Typ. Max. 20 20 mS tSYS1 tSYS1 tSYS1 nS Unit
1. tSYS is one of 1/fXIN main clock operation mode,
1/fXIN
tMCPW
tMCPW VDD-0.5V
XIN
tMRCP tMFCP
0.5V
tIW
tIW
INT1 ~ 3
0.8VDD 0.2VDD
tRST
RESET
0.2VDD
tECW
tECW 0.8VDD 0.2VDD
EC2, EC3
tREC
tFEC
Figure 7-1 Timing Chart
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7.5 A/D Converter Characteristics
(TA=25C, VDD=5V, VSS=0V)
Specifications Parameter Analog Input Voltage Range Overall Accuracy Non Linearity Error Differential Non Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time Symbol VAN CAIN NNLE NDNLE NZOE NFSE NGE TCONV Condition Min. fMAIN=4MHz VSS-0.3 Typ. 1.5 1.5 1.5 0.5 0.75 1.5 Max. VDD+0.3 2.5 2.5 2.5 2.0 1.0 2.0 15 S LSB V Unit
November 2001 Ver 1.1
17
HMS81C4x60
7.6 Typical Characteristics
These graphs and tables are for design guidance only and are not tested or guaranteed.
In some graphs or tables, the datas presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
IOH-VOH, VDD=5.2V
IOH (mA) -16 -14 -12 -10 -8 -6 -4 -2 0
2.0 3.0 4.0 5.0
-20C 25C 70C
IOL (mA) 40
IOL-VOL, VDD=5.2V
-20C 25C 70C
30
20
10
VOH (V)
1.0
2.0
3.0
4.0
VOL (V)
VDD-VIH
VIH1 (V) 4 3 2 1 0 4 4.5 5 5.5 VDD 6 (V) fMAIN=4MHz Ta=25C VIH2 (V) 4 3 2 1 0
VDD-VIH
Hysterisis
fMAIN=4MHz Ta=25C
4
4.5
5
5.5
VDD 6 (V)
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VDD-VIL
VIL1 (V) fMAIN=4MHz Ta=25C VIL1 (V)
VDD-VIL
Hysterisis
fMAIN=4MHz Ta=25C
3
3
2
2
1 4 4.5 5 5.5
VDD 6 (V)
1 4 4.5 5 5.5
VDD 6 (V)
Operating Area
fMAIN (MHz) Ta= -20~70C (Main-clock) 6 5 4 3 2 30 1 0 4 4.5 5 5.5 6 VDD 6.5 (V) 20 50 40 IDD (mA) 60
Normal Mode (Main opr.) IDD1-VDD
Ta=25C fMAIN=4MHz
4
4.5
5
5.5
VDD 6 (V)
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HMS81C4x60
8. MEMORY ORGANIZATION
The GMS81C4x60 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 60K bytes of Program memory. Data memory can be read and written to up to 1024 bytes including the stack area. Font memory has prepared 32K bytes for OSD.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address (00H ~ FFH) 15 1 8 7 SP 0
Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used.
Figure 8-1 Configuration of Registers
Hardware fixed
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y
Y A
Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP
LDX TXSP #0FFH ; SP FFH
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).
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[Zero flag Z] This flag is set when the result of an arithmetic operation
MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR BRK FLAG
or data transfer is "0" and is cleared by any other result.
LSB
N
V
G
B
H
I
Z
C
RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G]
This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR register (address 0F3H). It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7FH) or -128 (80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
November 2001 Ver 1.1
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HMS81C4x60
At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RETI instruction
01BC 01BD 01BE 01BF PCL PCH Push down
01BC 01BD 01BE 01BF PSW PCL PCH Push down
01BC 01BD 01BE 01BF PCL PCH Pop up
01BC 01BD 01BE 01BF PSW PCL PCH Pop up
SP before execution SP after execution
01BF 01BD
01BF 01BC
01BD 01BF
01BC 01BF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01BC 01BD 01BE 01BF A Push down
At execution of POP instruction POP A (X,Y,PSW) 01BC 01BD 01BE 01BF A Pop up 01BFH 0100H
Stack depth
SP before execution SP after execution
01BF 01BE
01BE 01BF
Figure 8-4 Stack Operation
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 60K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 15 : : ;1BYTE INSTRUCTION ;INSTEAD OF 2 BYTES ;NORMAL CALL
1000H
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA INTERRUPT VECTOR AREA
PCALL AREA
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 1, for example, is assigned to location 0FFF8H. The interrupt service locations spaces 2-byte interval: 0FFF6H and 0FFF7H for External Interrupt 2, 0FFE8H and 0FFE9H for External Interrupt 3, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Address 0FFE0H I2C Vector Area Memory Bus Interface Interrupt Vector Basic Interval Timer Interrupt Vector Watchdog Timer Interrupt Vector External Interrupt 3/4 Vector Timer/Counter 3 Interrupt Vector Timer/Counter 1 Interrupt Vector V-Sync Interrupt Vector Slicer Interrupt Vector Timer/Counter 2 Interrupt Vector Timer/Counter 0 Interrupt Vector External Interrupt 2 Vector External Interrupt 1 Vector On Screen Display Interrupt Vector RESET Vector
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7.
E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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HMS81C4x60
Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (256 Bytes)
0FFFFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010 Reverse
~ ~ ~ ~
0D125H NEXT
~ ~
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH DH 6H
0FF00H 0FFD6H 25 D1
A
A
0FFFFH
0FFD7H 0FFFFH
A : index address
24
November 2001 Ver 1.1
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H I2C_INT NOT_USED BIT_INT WDT_INT IR_INT TIMER3 TIMER1 VSYNC_INT SLICE_INT T2_INT T0_INT EXT2_INT EXT1_INT OSD_INT NOT_USED RESET 0F000H
;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ;Disable All Interrupts CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0FFH ;Stack Pointer Initialize TXSP ; LDM PLLC,#0000_0101b ;16MHz system clock ; LDM R0, #0FFh ;Normal Port 0 LDM R0DIR,#0FFh ;Normal Port Direction : : LDM TM0,#0000_0000B ;timer stop : : CALL VRAM_CLR ;Clear VRAM : :
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HMS81C4x60
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and OSD memory.
0000H RAM (192 bytes) 00C0H 0100H 0200H RAM (256 bytes) 0300H RAM (256 bytes) 0400H 0440H 0500H NOT USED 0600H RAM (Slicer RAM) ( 256 Byte) Not Used 0A00H OSD RAM (192 bytes) 0AC0H 0B00H Peripheral Reg. (32 bytes) OSD RAM (192 bytes) PageB PageA Page5 Page6 RAM (64 bytes) Page4 NOT USED Page3 Page2 Page0 Peripheral Reg. (64 bytes) RAM (256 bytes) Stack area Page1
in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM CKCTLR,#05H ;Divide ratio / 8
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 22.
0700H
0BC0H Peripheral Reg. (32 bytes) 0C00H NOT USED 0FFFH
Address 00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C6H 00C7H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH 00CEH 00CFH
Symbol R0 R0DD R1 R1DD R2 R2DD R3 R3DD R4 R4DD reserved reserved reserved reserved FUNC PLLC
R/W R/W W R W R/W W R/W W R/W W W W
Reset Value ???????? 00000000 ???????? ---00000 ???????? --000000 ???????? 00000000 ???????? ----0000 0000000-0000000
Addressin g mode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte
Figure 8-8 Data Memory Map
User Memory The GMS81C4x60 has 1,024 x 8 bits for the user memory (RAM) except Peripheral Reg. (64 bytes) . Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained
Table 8-1Control registers
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0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DEH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH
TM0 TM2 TDR0 TDR1 TDR2 TDR3 BITR CKCTLR WDTR ICAR ICDR ICSR ICCR reserved reserved reserved PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5H PWMR5L reserved reserved reserved PWMCR1 PWMCR2 reserved reserved reserved AIPS ADCM ADR IEDS IMOD IENL IRQL IENH IRQH reversed IDCR IDFS IDR DPGR TMR reserved reserved
R/W R/W R/W R/W R/W R/W R W W R/W R/W R/W R/W W W W W W R/W R/W R/W R/W W R/W R W R/W R/W R/W R/W R/W R/W R R R/W W -
-0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 000100000000000 ???????? ???????? ???????? ???????? ???????? ???????? --?????? 00000000 -----000 --000000 ???????? ???????? --000000 --000000 00000000 00000000 00000000 00000000 0000-000 1----001 ???????? ----0000 ???????? -
byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte byte, bit byte, bit byte, bit byte byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte -
0AD0 0AD1 0AD2 0AD3 0AD4 0AD5 0AD6 0AD7 0AD8 0AD9 0ADA 0ADB 0ADC 0ADD 0ADE 0ADF 0AE0H 0AE1H 0AE2H 0AE3H 0AE4H 0AE5H 0AE6H 0AE7H 0AE8H 0AE9H 0AEAH 0AEBH 0AECH 0AEDH 0AEEH 0AEFH 0AF0H 0AF1H 0AF2H 0AF3H 0AF4H 0AF5H 0AF9H 0BE0H 0BE1H 0BE2H 0BE3H 0BE4H 0BE7H 0BE8H
RED0 RED1 RED2 GREEN0 GREEN1 GREEN2 BLUE0 BLUE1 BLUE2 reserved reserved reserved reserved reserved reserved reserved OSDCON1 OSDCON2 OSDCON3 FDWSET EDGECOL CHEDCL OSDLN LHPOS DLLMOD DLLTST L1ATTR L1EATR L1VPOS L2ATTR L2EATR L2VPOS WINSH WINSY WINEH WINEY VCNT HCNT CULTAD SLCON SLINF0 SLINF1 RIKST RIKED SNCST SNCED
W W W W W W W W W R/W R/W W W W W R W W R W W W W W W W W W W R R W R/W W W W W W W
???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? 00000000 00000000 00000000 01111010 10000111 ???????? ---00000 ???????? 00000000 --000000 ??????-? ---????? ???????? ???????? ---????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? 00000000 00000000 00000000 ???????? ???????? ???????? ????????
byte, bitbyte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte, bit byte, bit byte byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte, bit byte, bit byte, bit byte byte byte byte
Table 8-1Control registers
1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
Table 8-1Control registers
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8.4 Addressing Mode
The GMS81C4x60 uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
35H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0
E551: C535 LDA 35H ;A RAM[35H]
A
~ ~ ~ ~
C5 35
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
FE0435 ADC #35H
MEMORY
data A
0E550H 0E551H
: direct page
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
F100: 0735F0 ADC !0F035H ;A ROM[0F035H]
04 35
A+35H+C A
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=01H
E45535 LDM 35H,#55H ~ ~
0F100H 0F101H 0135H data data 55H 0F102H 07 35 F0 address: 0F035 0F035H data
A
~ ~
A+data+C A
~ ~
~ ~
0F100H 0F101H 0F102H E4 55 35
A
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
F100: 981501 INC !0115H ;A ROM[115H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
F100: DB LDA {X}+
115H
data
A
~ ~
~ ~
0F100H 0F101H 0F102H 98 15 01
A
data+1 data
35H
data
A
~ ~
data A
~ ~
DB
address: 0115
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H
E550: D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
E550: C645 LDA 45H+X
115H
data
A
~ ~
data A
~ ~
0E550H D4
3AH
data
A
~ ~
0E550H 0E551H C6 45
~ ~
A
data A
45H+0F5H=13AH
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HMS81C4x60
Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
F100: D500FA LDA !0FA00H+Y
FA00: 3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
A jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] A
data A
~ ~
0FA55H data
~ ~
Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
FA00: 1625 ADC [25H+X]
A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~A ~
0E005H
~ ~
25 + X(10) = 35H
~ ~
16 25
A A + data + C A
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Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
FA00: 1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
FA00: 1F25E0 JMP [!0E025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
A
0E005H + Y(10) = 0E015H
~ ~
~ ~
NEXT
A
jump to address 0E725H
~ ~
0E725H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25
~ ~
A A + data + C A
E0
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HMS81C4x60
9. I/O PORTS
The HMS81C4x60 has 5 ports (R0, R1, R2, R3 and R4) and OSD ports (R,G,B,YS,YM). These ports pins may be multiplexed with an alternatefunction for the peripheral features on the device. In general, in an initial reset state, R ports are used as a general purpose digital port.
9.1 Registers for Port
Port Data Registers The Port Data Registers (R0, R1, R2, R3, R4) are represented as a D-Type flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal. Port Direction Registers All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1. All the port direction registers in the HMS81C4x60 have been written to zero by reset function. On the other hand, its initial status is input.
WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H R0 DATA R0 DIRECTION 01010101 76543210 BIT
~ ~
0C8H 0C9H R4 DATA R4 DIRECTION
~ ~
01010101 76543210 BIT
I O I O I O I O PORT 76543210 I : INPUT PORT O : OUTPUT PORT
Figure 9-1 Example of port I/O assignment
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9.2 I/O Ports Configuration
R0 Ports R07 ~ R04 is an open drain bidirectional I/O port and R03 ~ R00 is a CMOS bidirectional I/O port(address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). The control registers for R0 are shown below.
R0 Data Register
R/W R/W R/W R/W
functions as following table.
Port Pin R10 R11 R12 R13 R14 Alternate Function AN0 (A/D input 0) AN1 (A/D input 1) AN2 (A/D input 2) AN3 (A/D input 3) AN4 (A/D input 4)
ADDRESS : 00C0H RESET VALUE : Undefined
R/W R/W R/W R/W
R0
R07
R06
R05
R04
R03
R02
R01
R00
R0 Direction Register
W W W W
ADDRESS : 00C1H RESET VALUE : 0000 0000b
W W W W
Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, this value is "0", port may be used as normal input port. The way to select alternate function such as comparator input will be shown in each peripheral section. In addition, R1 port is used as key scan function which operate with normal input port. Input or output is configured automatically by each function register (KSMR) regardless of R1DD. R2 Port R2 is a 6-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 00C5H).The control registers for R2 are shown below.
R2 Data Register
R/W R/W R/W R/W
R0DD
Port Direction 0: Input 1: Output
R1 Ports R1 is a 5-bit CMOS input port only(address 0C2H). Each pin can independently used as an input through the R1DD register (address 0C3H). User can use R0DD register when its bit is 0 only. The control registers for R1 are shown below.
R1 Data Register
R R R R
ADDRESS : 00C4H RESET VALUE : Undefined
R/W R/W R/W R/W
ADDRESS : 00C2H RESET VALUE : Undefined
R R R R
R2
R25
R24
R23
R22
R21
R20
R1
R14
R13
R12
R11
R10 R2 Direction Register ADDRESS : 00C5H RESET VALUE : 0000 0000b
W W W W W W
R1 Direction Register
W W W W
ADDRESS : 00C3H RESET VALUE : ---0 0000b
W W W W
W
W
R2DD
-
Port Direction 0: Input 1: Output ADDRESS: 00CEH INITIAL VALUE: 0000 0000b
R1DD
-
-
Port Direction 0 : use Input only
W
W -
W
W
ADDRESS: 00EFH INITIAL VALUE: --00 0000H W W W W LSB AIPS.5 ~ AIPS.0 0 : R0 Port 1 : ADC Input
W
W -
W EC 3S
W EC 2S
W
W
W
W 1 LSB
FUNC
MSB
-
IN T3S IN T2S IN T 1S
AIPS
MSB
-
AIPS5 AIPS4 AIPS3 AIPS2 AIPS1 AIPS0
FUNC.5 ~ FUNC.1 0 : R2 Port 1 : INT mode, EC mode
user m ust set 1
R1 port also can use the value bit5 ~ bit0 of AIPS register to secondary function register. R1 port have secondary
R2 port also use the value bit5 ~ bit1 of FUNC register to secondary function register. R2 port have secondary func-
November 2001 Ver 1.1
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HMS81C4x60
tions as following table.
Port Pin R21 R22 R23 R24 R25 Alternate Function INT1 (External Interrupt 1) INT2 (External Interrupt 2) INT3 (External Interrupt 3) EC2 (Event Counter 2) EC3 (Event Counter 3)
R4 Port R4 is a 4-bit open drain and bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0C9H). The control registers for R4 are shown below.
R4 Data Register
R/W R/W R/W R/W
ADDRESS : 00C8H RESET VALUE : Undefined
R/W R/W R/W R/W
R3 Port R3 is a 8-bit CMOS bidirectional output port (address 0C6H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0C7H). The control registers for R3 are shown below.
R3 Data Register
R/W R/W R/W R/W
R4
R43
R42
R41
R40
R4 Direction Register
W W W W
ADDRESS : 00C9H RESET VALUE : 0000 0000b
W W W W
R4DD
-
-
-
Port Direction 0: Input 1: Output ADDRESS: 00DBH INITIAL VALUE: 0000 0000b
ADDRESS : 00C6H RESET VALUE : Undefined
R/W R/W R/W R/W
R3
R37
R36
R35
R34
R33
R32
R31
R30 R/W R/W R/W R/W ESO
R/W CCR3
R/W
R/W
R/W LSB
R3 Direction Register
W W W W
ADDRESS : 00C7H RESET VALUE : 0000 0000b
W W W W
ICCR
BSEL1 BSEL0 AC Kb MSB
C C R 2 C CR 1 C C R0
R3DD
Port Direction 0: Input 1: Output ADDRESS: 00EAH INITIAL VALUE: 0000 0000b R/W R/W BU Z R/W EN 5 R/W EN 4 R/W EN 3 R/W EN 2 R/W EN 1 R/W E N0 LSB PWMCR.7 ~ PWMCR.0 0 : R3 Port 1 : PWM, BUZ, TMR1
ICCR.7 ~ ICCR.6 00 : R4 Port 01 : SCL0, SDA0, R42, R43 10 : SCL1, SDA1, R40, R41 11 : SCL0, SDA0, SCL1, SDA1
R4 port also use the value bit7 ~ bit6 of ICCR register to secondary function register. R4 port have secondary functions as following table.
R40 R41 R42 R43 SCL0 (Serial Clock 0) SDA0 (Serial Data 0) SCL1 (Serial Clock 1) SDA1 (Serial Data 1)
PWMCR1
TM R 1
MSB
R3 port also use the value bit7 ~ bit0 of PWMCR1 register to secondary function register. R3 port have secondary functions as following table.
R30 R31 R32 R33 R34 R35 R36 R37 PWM0 (Pulse Width Modulation 0) PWM1 (Pulse Width Modulation 1) PWM2 (Pulse Width Modulation 2) PWM3 (Pulse Width Modulation 3) PWM4 (Pulse Width Modulation 4) PWM5 (Pulse Width Modulation 5 - 14bit) BUZ (Buzzer Output) TMR1 (Timer Interrup 1)
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HMS81C4x60
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generation Circuit consist PLL that generate multiplicated frequency of Crystal clock, Generation Circuit which create CPU clock, Prescaler which generate input clock of Basic Interval Timer and variable hardware clock, Basic Interval timer which is generate standard time, Watch Dog Timer which is protect Software Overflow. See "12.1 BASIC INTERVAL TIMER" on page for details.
Data Slicer Clock OSD Clock
OSC Circuit
PLL
Clock Pulse Generator
Internal System Clock (16MHz typical)
PRESCALER (11) ENPCK 11 8 0 MUX Basic Interval Timer(8) BTCL 7 0 Watch Dog Timer(6) 6 COMPARATOR 6 WDTON 0 CKCTRL 012345 6 8 WDTR 7 5 to RESET CIRCUIT 6 WDTCL IFWDT 5 Peripheral Circuit IFBIT WDTCL
Internal DATA BUS
10.1 Clock Generation Circuit
The clock signal come from crystal oscillator or ceramic via Xin and Xout or from external clock via Xin is supplied to Clock Pulse Generator and Prescaler. Internal System Clock for CPU is made by Clock Pulse Generator, and several peripherial clock is divided by prescaler. Clock Generation circuit of Crystal Oscillator or Ceramic Resonator is shown as below.
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Cout Xout
Xout
Open
Xin Cin
GND
Xin
External Clock
Figure 10-1 Cristal Oscillator or Ceramic Resonator
Figure 10-2 External Clock
10.2 Phase Locked Loop
PLL(Phase Locked Loop) from OSC 4MHz clock circuit generate Internal System clock, Timer clock(PS0), Data Slicer Clock, OSD clock, etc.
Figure 10-3 PLL Control Register
W W W W W PC F2 W PC F1 W W LSB PLL clock frequency 0 : Off PLL 1 : On PLL, in the case system clock supply OSD circuit PLL clock frequency 000 : 8MHz 001 : 12MHz 010 : 16MHz(typical) 011 : 24MHz 100 : 32Mhz Test mode
PLLC
MSB
-
PCF 0 PLLO N
ADDRESS: 00CFH INITIAL VALUE: -000 0000b
10.3 PRESCALER
Prescaler consistor of 11-bit binary counter, and input clock which is supplied by oscillation circuit. Frequency divided by prescaler is used as a source clock for peripherial hardwares.
fex
PS1
PS2
PS3 PS4
PS5
PS6
PS7
PS8
PS9
PS10 PS11
ENPCK
B.I.T 8 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 12 PERIPHERAL
Figure 10-4 Prescaler
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Peripheral Clock supplied from prescaler can be stopped by ENPCK. Peripheral clock is determined by CKCTLR
Register.(However, PS11 cannot be stopped by ENPCK)
W
W -
W
W
W
W BTS2
W BTS1
W BTS 0 LSB
CKCTLR
MSB
-
W D TO N EN PC K BT CL
ADDRESS: 00F6H INITIAL VALUE: --00 0000b B.I.T input clock select 000 : PS4 (4S) 001 : PS5 (8S) 010 : PS6 (16S) 011 : PS7 (32S) 100 : PS8 (64S) 101 : PS9 (128S) 110 : PS10 (256S) 111 : PS11 (512S) B.I.T clear (when write) 0 : B.I.T Free-run 1 : B.I.T clear (Auto reset when after 1 cycle) Peripherial clock enable (when write) 0 : Peripherial clock stop 1 : Peripherial clock supply WDT function control(when write) 0 : 6 bit TIMER 1 : WATCH-DOG TIMER B.I.T value (when read) data : 00h ~ FFh
Figure 10-5 Clock Control Register
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11. INTERRUPTS
The HMS81C4x60 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH and IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 16 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 11-2. Below table shows the Interrupt priority
Reset/Interrupt Hardware Reset reserved OSD Interrupt External Interrupt 1 External Interrupt 2 Timer/Counter 0 Timer/Counter 2 Slicer Interrupt VSync Interrupt Timer/Counter 1 Timer/Counter 3 Interrupt interval measure Watchdog Timer Basic Interval Timer reserved I2C Interrupt Symbol RESET OSD INT1 INT2 Timer 0 Timer 2 Slicer VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT I2C Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Interrupt Mode Register It controls interrupt priority. It takes only one specified interrupt. Of course, interrupt's priority is fixed by H/W, but sometimes user want to get specified interrupt even if higher priority interrupt was occured. Higher priority interrupt is occured the next time. It contains 2bit data to enable priority selection and 4bit data to select specified interrupt.
Bit No. Name Value 00 01 1X 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function Mode 0: H/W priority Mode 1: S/W priority Interrupt is disabled, even if IE is set. OSD INT1 INT2 Timer 0 Timer 2 Slicer VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT I2C Not used
5,4
IM1~0
3~0
IP3~0
The External Interrupts can be transition-activated (1-to-0 or 0-to-1 transition). When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. T he Timer/Co un ter In ter ru p ts a r e gen e rated by TnIF(n=0~3), which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), that is the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH,IRQL) except Power-on reset and software BRK interrupt.
Table 11-1 Bit function
Interrupt Mode Register
R/W R/W R/W R/W
ADDRESS : 00F3H RESET VALUE : Undefined
R/W R/W R/W R/W
IMOD
M1
M0
IP3
IP2
IP1
IP0
Figure 11-1 Interrupt Mode Register
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Internal bus line
IENH [00F6H] IRQH [0F7H]
-
Interrupt Enable Register (Higher byte)
IMOD [00F3H]
Bit5
IFOSD INT1 INT2 Timer 0 Timer 2 Slicer IFVSync
OSD
RESET
INT1
BRK
INT2 T0 T2 SLICE VSync T1 T3 INTV WDT BIT -
To CPU
Priority Control
I Flag Interrupt Master Enable Flag
I-flag is in P SW , it is cleared by "D I", set by "EI" instruction. W hen it goes interrupt service, I-flag is cleared by hardw are, thus any other interrupt are inhibited. W hen interrupt service is com pleted by "R ETI" instruction, I-flag is set to "1" by hardw are.
Timer 1 Timer 3 Intr. interval IFWDT IFBIT
IFI2C IRQL [00F5H]
I2C
Interrupt Vector Address Generator IENL [00F4H]
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 11-2 Block Diagram of Interrupt
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Interrupt request flag registers are shown in Figure 11-3. Interrupt request is generated when suitable bit is set, and suitable request flag of accepted interrup is clear when interrupt processing cycle. Suitable bit is set when interrupt
R/W R/W R/W R/W INT2 R/W T0 R/W T2 R/W
request is occured, but no accepted request flag is set to hold when the interrupt is accepted. Also, interrupt request flag register(IRQH, IRQL) is the register of read or write. So, request flag can be changed by program.
R/W LSB VSync interrupt request flag Slicer interrupt request flag Timer / Counter 2 interrupt request flag Timer / Counter 0 interrupt request flag External interrupt 2 interrupt request flag External interrupt 1 interrupt request flag On screen display interrupt request flag
IRQH
MSB
-
OSD INT1
SLICE VSync
ADDRESS: 00F7H INITIAL VALUE: 0000 0000b
R/W
R/W T3
R/W INTV
R/W WDT
R/W BIT
R/W -
R/W I2C LSB
IRQL
T1 MSB
ADDRESS: 00F5H INITIAL VALUE: 0000 000-b I2C interrupt request flag
Basic interval timer interrupt request flag Watch-dog timer interrupt request flag Interrupt interval measurement interrupt request flag (INT3/4) Timer / Counter 3 interrupt request flag Timer / Counter 1 interrupt request flag
Figure 11-3 Interrupt Request Flag Registers
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Interrupt enable flag registers are shown in Figure 11-4. These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0",
R/W R/W R/W R/W INT2 R/W T0 R/W T2 R/W
a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
R/W LSB
IENH
MSB
-
OSD INT1
SLICE VSync
ADDRESS: 00F6H INITIAL VALUE: 0000 0000b VSync interrupt enable flag Slicer interrupt enable flag Timer / Counter 2 interrupt enable flag Timer / Counter 0 interrupt enable flag External interrupt 2 interrupt enable flag External interrupt 1 interrupt enable flag On screen display interrupt enable flag
R/W
R/W T3
R/W INTV
R/W WDT
R/W BIT
R/W -
R/W I2C LSB
IENL
T1 MSB
ADDRESS: 00F4H INITIAL VALUE: 0000 000-b I2C interrupt enable flag
Basic interval timer interrupt enable flag Watch-dog timer interrupt enable flag Interrupt interval measurement interrupt enable flag (INT3/4) Timer / Counter 3 interrupt enable flag Timer / Counter 1 interrupt enable flag
Figure 11-4 Interrupt Enable Flag Regesters
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11.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 f ex (2 s at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decrements 3 times. 4. The entry address of the interrupt service program is read from the vector table address, and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.
System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 11-5 Interrupt Service routine Entering Timing
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Basic Interval Timer Vector Table Address
Entry Address
General-purpose register save/restore using push and pop instructions;
0FFE6H 0FFE7H
012H 0E3H
0E312H 0E313H
0EH 2EH
main task acceptance of interrupt interrupt service task saving registers
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. restoring registers interrupt return
A maskable interrupt is not accepted until the I-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the I-flag is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
11.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which is the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 11-6.
Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions
INTxx: PUSH PUSH LDA PUSH A X DPGR A ;SAVE ACC. ;SAVE X REG. ;SAVE DPGR ; Direct page ; accessable reg. ;
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
TCALL0 ROUTINE
RET
: interrupt processing :
Figure 11-6 Execution of BRK/TCALL0
POP STA POP POP RETI
A DPGR X A
;RESTORE DPGR ;RESTORE X REG. ;RESTORE ACC. ;RETURN
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11.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Main Program service
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER 1 service INT0 service
enable INT0 disable other EI
Occur TIMER1 interrupt
Occur INT0
TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI
A X Y IENH,#20H IENL,#0
;Enable INT1 only ;Disable other ;Enable Interrupt
enable INT0 enable other
IENH,#FFH IENL,#FEH Y X A
;Enable all interrupts
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 11-7 Execution of Multi Interrupt
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11.4 External Interrupt
The external interrupt on INT1, INT2... pins are edge triggered depending the edge selection register. Refer to "6. PORT STRUCTURES" on page 12. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. INT1, INT2 and INT3 are multiplexed with general I/O ports. To use external interrupt pin, the bit of port function register FUNC1 should be set to "1" correspondingly.
Response Time The INT1, INT2 and INT3 edge are latched into INT1IF, INT2IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. For example, the DIV instruction takes twelve machine cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine
INT1 pin
INT1IF
INT1 INTERRUPT
edge selection
INT2 pin
INT2IF
INT2 INTERRUPT
INT3 pin
INT3IF
INT3 INTERRUPT
IEDS [00F2H]
Figure 11-8 External Interrupt Block Diagram
System clock
Instruction Fetch Last instruction execution (0~12cycle) Interrupt request sampling 1cycle Interrupt overhaed (9~21cycle) Enter interrupt service routine (8cycle)
Figure 11-9 Interrupt Response Timing Diagram ( Interrupt overhead )
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12. TIMER
12.1 Basic Interval Timer
The HMS81C4x60 has one 8-bit Basic Interval Timer that is free-run and can not be stopped. Block diagram is shown in Figure 12-1. The Basic Interval Timer generates the time base for watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 12-2. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 00D6H is read as a BITR and written to CKCTLR..
PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11
fex/210 fex/211
fex/24 fex/25 fex/26 fex/27 fex/28 fex/29
MUX
source clock
8-bit up-counter overflow
BITR
[0D6H]
BITIF
Basic Interval Timer Interrupt
Watchdog timer clock (WDTCK)
clear 3 BITCK
BTCL
Select Input clock Clock control register [0D6H] CKCTLR
WDT ENPCK BTCL BTS2 BTS1 BTS0 ON
Internal bus line
Figure 12-1 Block Diagram of Basic Interval Timer
W
W -
W
W
W
W BTS2
W BT S1
W BT S0 LSB
CKCTLR
MSB
-
W D TO N ENP CK BTC L
ADDRESS: 00D6H INITIAL VALUE: --00 0000b B.I.T Clock B.I.T clear (when write) 0 : B.I.T Free-run 1 : B.I.T clear (Auto reset when after 1 cycle)
Caution:
Peripherial clock enable (write time) 0 : Peripherial clock stop 1 : Peripherial clock supply WDT function control 0 : 6 bit TIMER 1 : WATCH-DOG TIMER B.I.T value (when read)
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. R R R R R R R R
BITR
MSB 8-BIT BINARY COUNTER LSB
ADDRESS: 00D6H INITIAL VALUE: Undefined
Figure 12-2 BITR Basic Interval Timer Mode Register
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12.2 Timer 0, 1
Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 12-3 and Figure 12-4. These Timers can run separated 8bit timer or combined 16bit timer. These timers are operated by internal clock. The contents of TDR1 are compared with the contents of up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared.
Note: You can read Timer 0, Timer 1 value from TDR0 or TDR1. But if you write data to TDR0 or TDR1, it changes Timer 0 or Timer 1 modulo data, not Timer value.
The content of TDR0, TDR1 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 0 or Timer 1 can not count up forever. The control registers for Timer 0,1 are shown below.
R/W
R/W T 1ST
R/W
R/W
R/W T 0ST
R/W
R/W
R/W LSB
TM0
MSB
-
T1SL1 T1SL0
T 0C N T 0SL1 T 0SL0
ADDRESS: 00D0H INITIAL VALUE: -000 0000b
T0 input clock select(fex=4MHz) 00 : PS2(1S) 01 : PS4(4S) 10 : PS6(16S) 11 : PS8(64S) Timer 0 Continue/Hold control 0 : Count Hold 1 : Count Countinue Timer 0 Start control 0 : Count Hold 1 : Count Clear and Start Timer 1 input clock(fex=4MHz) 00 : Timer 0 overflow (16bit mode) 01 : PS2(1S) 10 : PS4(4S) 11 : PS6(16S) Timer 1Start/Hold control 0 : Count Hold 0 : Count Clear and Start ADDRESS: 00D2H R/W R/W R/W R/W INITIAL VALUE: Undefined R/W R/W R/W R/W LSB ADDRESS: 00D3H INITIAL VALUE: Undefined R/W R/W R/W R/W LSB
TDR0
MSB
R/W
R/W
R/W
R/W
TDR1
MSB
Figure 12-3 Timer / Event Count 0,1 (Example) TIMER0 1mS TIME INTERVAL INTERRUPT : : TDR_CNT: LDM TDR0,#249 LDM TDR1,#0 LDM TM0,#0011_1101b ; 4uSEC PRESCALER FOR T0 : :
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.
Internal bus line TM0 TDR0 TDR1
T0CN
8bit Comparator
T0IF Timer 0 Timer 1
8bit Comparator
T1IF
PS2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
NC PS2 PS4 PS6
MUX
T1ST
Figure 12-4 Simplified Block Diagram of 8bit Timer0, 1
TDR0
disable enable
clear & start stop
up
-c
ou n
t
~ ~
~ ~
TIME Timer 0 (T0IF) Interrupt
Occur interrupt Occur interrupt
T0ST Start & Stop
T0ST = 0
T0ST = 1
T0CN Control count
T0CN = 0
T0CN = 1
Figure 12-5 Count Example of Timer
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Internal bus line TM0 0 0 T0CN TDR0 TDR1
16bit Comparator
T1IF Timer 0 Timer 1
PS2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
Figure 12-6 Simplified Block Diagram of 16bit Timer0, 1
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12.3 Timer / Event Counter 2, 3
Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 12-7 and Figure 12-8. These Timers have two operating modes. One is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin R24/EC2, R25/EC3. These Timers can run separated 8bit timer or combined 16bit timer.
Note: You can read Timer 2, Timer 3 value from TDR2 or TDR3. But if you write data to TDR2 or TDR3, it changes Timer 2 or Timer 3 modulo data, not Timer value.
The content of TDR2, TDR3 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 2 or Timer 3 can not count up forever. The control registers for Timer 2,3 are shown below
R/W
R/W T3ST
R/W
R/W
R/W T3ST
R/W
R/W
R/W LSB
TM2
MSB
-
T 3SL1 T 3SL0
T3C N T3SL1 T3SL0
ADDRESS: 00D1H INITIAL VALUE: -000 0000b
T2 input clock select 00 : External EVENT input(EC2) 01 : PS2(1S) 10 : PS4(4S) 11 : PS6(16S) Timer 2 Continue/Hold control 0 : Count Hold 1 : Count Countinue Timer 2 Start/Hold control 0 : Count Hold 1 : Count Clear and Start Timer 3 input clock 00 : Connected to T2(16bit mode) 01 : External EVENT input(EC3) 10 : PS2 (1S) 11 : PS6 (16S) Timer 3 Start/Hold control 0 : Count Hold 0 : Count Clear and Start ADDRESS: 00D4H R/W R/W T DR 6 R/W TD R 5 R/W TD R 4 INITIAL VALUE: Undefined R/W R/W R/W R/W TD R 3 TD R 2 T D R1 TD R 0 LSB ADDRESS: 00D5H INITIAL VALUE: Undefined R/W R/W R/W R/W TD R 3 TD R2 TD R 1 TD R 0 LSB W W W EC 1S W EC 0S W W W W LSB R24/EC2 Select 0 : R24 1 : EC2 R25/EC3 Select 0 : R25 1 : EC3
TDR2
T DR 7 MSB
R/W
R/W TD R 6
R/W TD R 5
R/W TD R 4
TDR3
TD R 7 MSB
FUNC
MSB
-
IN T 3S IN T 2S IN T1S
ADDRESS: 00CEH INITIAL VALUE: 0000 000-b
Figure 12-7 Timer / Event Count 2,3
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.
Internal bus line TM2 TDR2 TDR3
T2CN
8bit Comparator
T2IF Timer 2 Timer 3
8bit Comparator
T3IF
EC2 PS2 PS4 PS6
MUX Clock T2ST Clear Clock Clear
NC EC3 PS2 PS4
MUX
T3ST
Figure 12-8 Simplified Block Diagram of 8bit Timer/Event Counter 2,3
TDR2
disable enable
clear & start stop
up
-c o
un
t
~ ~
~ ~
TIME Timer 2 (T2IF) Interrupt
Occur interrupt Occur interrupt
T2ST Start & Stop
T2ST = 0
T2ST = 1
T2CN Control count
T2CN = 0
T2CN = 1
Figure 12-9 Count Example of Timer / Event counter
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Internal bus line TM2 0 0 T0CN TDR2 TDR3
16bit Comparator
T3IF Timer 2 Timer 3
EC2 PS4 PS6 PS8
MUX Clock T0ST Clear Clock Clear
Figure 12-10 Simplified Block Diagram of 16bit Timer/Event Counter 2,3
Timer Mode In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn (n=0~3) are compared with the contents of up-counter, Timer n. If match is found, a timer
n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you wantU
Start count
Source clock
~ ~ ~~~~ ~~~~
N-2 N-1 N 0 1 3 4
Up-counter
0
1
2
3
2
TDRn (n=0~3) TnIF (n=0~3) interrupt
N
Match Detect
Counter Clear
Figure 12-11 Timer Mode Timing Chart
~ ~
Event Counter Mode In event timer mode, counting up is started by an external trigger. This trigger means falling edge of the ECn (n=0~1 ) pin input. Source clock is used as an internal clock selected with TM2. The contents of TDRn are compared with the contents of the up-counter. If a match is found, an TnIF interrupt is generated, and the counter is cleared to 00H. The counter is restarted by the falling edge of the ECn pin in-
put. The maximum frequency applied to the ECn pin is fex/2 [Hz] in main clock mode. In order to use event counter function, the bit EC0S, EC1S of the Port Function Select Register FUNC(address 0CEH) is required to be set to "1". After reset, the value of TDRn is undefined, it should be
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initialized to between 01H~FFHS not to 00HU
Start count
ECn (n=2~3) pin
~ ~ ~~~~ ~~~~
Up-counter
0
1
2
N-1
N
0
1
2
TDRn (n=2~3) TnIF (n=2~3) interrupt
N
Figure 12-12 Event Counter Mode Timing Chart
~ ~
The interval period of Timer is calculated as below equation.
1Period = ----- x Prescaler ratio x TDR n fex
TDR2 TDR2=n
n n-1 n-2
t
PCP
~ ~
un
~ ~
-c o
8 7 6
up
~ ~
2 1 0
5 4 3
TIME
Interrupt period = PCP x n
Timer 2 (T2IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 12-13 Count Example of Timer / Event counter
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TDR2
disable enable
clear & start stop
up
-c o
un
t
~ ~
~ ~
TIME Timer 2 (T2IF) Interrupt
Occur interrupt Occur interrupt
T2ST Start & Stop
T2ST = 0
T2ST = 1
T2CN Control count
T2CN = 0
T2CN = 1
Figure 12-14 Count Operation of Timer / Event counter
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13. A/D Converter
The A/D converter circuit is shown in Figure 13-1. The A/D converter circuit consists of the comparator and c o n t r o l r e g i st e r A I P S ( 0 0 E F H ) , AD C M( 0 0F 0 H ) , ADR(00F1H). The AIPS register select normal port or anData Bus 5 0 ADCM [F0H]
ADEN ADS2 ADS1 ADS0 ADST ADSF
alog input. The ADCM register control A/D converter's activity. The ADR register stores A/D converted 8bit result. The more details are shown Figure 13-2.
8
ADR [F1H]
0
1
2
3
4 8
5
6
7
IFA Control circuit port select AN0 AN1 AN2 AN3 AN4 Register ladder 8 MUX Vref S/H
Comparator
+ -
Succesive Approximation Circuit
Figure 13-1 Block Diagram of A/D convertor circuit
Control The HMS81C4x60 contains a A/D converter module which has six analog inputs. 1. First of all, you have to select analog input pin by set the ADCM and AIPS. 2. Set ADEN (A/D enable bit : ADCM bit5). 3. Set ADST (A/D start bit : ADCM bit1). We recommend you do not set ADEN and ADST at once, it makes worse A/D converted result. 4. ADST bit will be cleared 1 cycle automatically after you set this. [Example]
;Set AIPS, change ? to what you want ; 0 : digital port ; 1 : analog port LDM AIPS,#0000_1000b ; Set ADEN, xxx is analog port number LDM ADCM,#0010_1100b ; or "SET1 ADEN" ; Set ADST, xxx is analog port number LDM ADCM,#0010_11110b
BBC ADCM.ADSF,$ LDA ADR ; or "SET1 ADST" : :
5. After A/D conversion is completed, ADSF bit and interrupt flag IFA will be set. (A/D conversion takes 36 machine cycle : 18uS when fex=4MHz).
Note: Make sure AIPS bits, if you using a port which is set digital input by AIPS, analog voltage will be flow into MCU internal logic not A/D converter. Sometimes device or port is damaged permanently.
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R/W
R/W -
R/W AD EN
R/W AD S2
R/W AD S1
R/W AD S0
R/W AD ST
R AD SF LSB
ADCM
MSB
-
ADDRESS: 00F0H INITIAL VALUE: --01 1101b A/D Converter Status bit 0 : Busy 1 : A/D conversion completed A/D Converter Start bit 0 : Ignore 1 : A/D start (`0' after 1 cycle) Analog Port Select 000 : AN0 select 001 : AN1 select 010 : AN2 select 011 : AN3 select 100 : AN4 select 101 : Default 110 : Default 111 : Default A/D Converter Enable bit 0 : Disable 1 : Enable
ADDRESS: 00F1H R R T DR 6 R T DR 5 R T DR 4 R INITIAL VALUE: Undefined R R R T DR 2 TD R1 TD R 0 LSB ADDRESS: 00EFH INITIAL VALUE: ---0 0000H W W W W LSB Analog Input Select 0 : P1 input 1 : ADC Input
ADR
T DR 7 MSB
T DR 3
W
W -
W -
W
AIPS
MSB
-
A IPS4 A IPS3 AIPS2 AIPS1 AIPS0
Figure 13-2 A/D convertor Registers
PORT select ADS2 ADS1 0 0 1 1 0 ADS0 Function AN0 AN1 AN2 AN3 AN4 R14/AN4 R14 R14 R14 R14 AN4 R13/AN3 R13 R13 R13 AN3 R13 R12/AN2 R12 R12 AN2 R12 R12 R11/AN1 R11 AN1 R11 R11 R11 R10/AN0 AN0 R10 R10 R10 R10
9 9
0 0 1
9 : 9 : 9
Figure 13-3 A/D Conversion Data Register
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14. Pulse Width Modulation (PWM)
The PWM circuit is shown in Figure 14-1, .
Example (fex=4MHz) Resolution Input Clock Frame cycle 14bit PWM 14 bits 2MHz 8,192uS 8bit PWM 8 bits 250KHz 1,024uS
PWMCR2 [EBH] PWMCR1 [EAH]
The PWM circuit consists of the counter, comparator, Data register. The PWM control registers are PWMR4~0, PWMCR2~1, PWM5H, PWM5L. The more details about registers are shown Figure 14-2 .
3 21 0
EN5 CNTB EN4 EN3 EN2 EN1 EN0
PWMR5 [E5H] PWMR4 [E4H] PWMR3 [E3H] PWMR2 [E2H] PWMR1 [E1H] PWMR0 [E0H]
EN5 EN4
PWM5 PWM4 PWM3
EN3
PWM2
EN2 EN1 EN0
PWM1
PWM0
8bit comparator
CNTB
PS5 8bit counter IF1Frame
Figure 14-1 8bit register (PWM7~0) circuit
Internal Control
PWMCR2 [EBH]
PWMCR1 [EAH]
CNT CNTB PWMR5L 6bit [E9H]
PWMR5H 8bit [E8 H]
EN8
PWM8 MSB 14bit comparator LSB
PS2 14bit counter
Figure 14-2 14bit register (PWM8) circuit
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8bit PWM Control The HMS81C4x60 contains a one 14bit PWM and five 8bit PWM module. 1. 8bit PWM0~5 is wholy same internal circuit, but PWM0~5 output port is CMOS bidirectional I/O pin. 2. Al l PWM polarity has the same by POL2's value. 3. Calulate Frame cycle and Pulse width is as following. PWM Frame Cycle = 213/ fex (Sec) PWM Width = (PWMRn+1) x 25 / fex (n=0~5) Pulse Duty (%) = (PWMRn +1) / 256 x 100(%) (n=0~5)
Sub PWM Frame Cycle = Main Frame Cycle / 64. 4. Table 14-1, "PWM5L and Sub frame matching table," on page 58 show PWM5L function.
Bit value if Bit0=1 if Bit1=1 if Bit2=1 if Bit3=1 if Bit4=1 Sub frame number which is added 1 clock 32 16, 48 8, 24, 40, 56 4, 12, 20, 28, 36, 44, 52, 60 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 Pulse count 1 2 4 8 16
Positive Polarity (POL2=0)
Negative Polarity (POL2=1)
if Bit5=1
1 2 1 2
32
Table 14-1 PWM5L and Sub frame matching table
1. Frame cycle 2. Pulse Width Main PWM Frame
Figure 14-3 Wave form example for 8bit PWM
012
61 62 63
.....
4. PWM output is enabled during ENn(n=0~5) bit (See PWMCR1~2) contains 1.
Sub PWM Frame
PWMR4~0
R/W MSB R/W R/W R/W
ADDRESS: 00E0H~E4H INITIAL VALUE: Undefined R/W R/W R/W R/W LSB
Sub PWM Frame which is added 1 clock
1 clock width : PS2
PW M0D7 PW M0D6 PW M0D5 PW M0D4 PW M0D3 PW M0D2 PW M0D1 PW M0D0 Each PWM Data Store
Figure 14-5 Wave form example for 14bit PWM
Figure 14-4 8bit PWM Registers
5. CNTB controls all PWM counter enable. If CNTB=0, than Counter is disabled. 14bit PWM Control 1. 14bit PWM's operation concept is not the same as 8bit PWM. 1 PWM frame contains 64 sub PWMs. PWM5H : Set sub PWM's basic Pulse Width. PWM5L : Number of sub PWM which is added 1 clock. 2. PWM polarity is selected by POL1's value. If POL1=0, Positive Polarity. 3. Calulate Frame cycle and Pulse width is as following. Main PWM Frame Cycle = 216/ fex (Sec).
PWM5H
R/W MSB R/W R/W R/W
ADDRESS: 00E8H INITIAL VALUE: Undefined R/W R/W R/W R/W LSB ADDRESS: 00E9H INITIAL VALUE: Undefined R/W R/W R/W R/W LSB
PWM 5H7 PW M5H6 PW M5H5 PW M5H4 PW M5H3 PW M5H2 PW M5H1 PW M5H0
PWM5L
R/W MSB R/W R/W R/W
PW M5L5 PW M5L4 PW M5L3 PW M5L2 PW M5L1 PW M5L0
Figure 14-6 PWM5H, PWM5L Register
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R/W
R/W BU Z
R/W EN 5
R/W EN 4
R/W EN 3
R/W EN 2
R/W EN 1
R/W E N0 LSB
PWMCR1
TM R 1
ADDRESS: 00EAH INITIAL VALUE: 0000 0000b R30/PWM0 Select 0 : R30 1 : PWM0 R31/PWM1 Select 0 : R31 1 : PWM1 R32/PWM2 Select 0 : R32 1 : PWM2 R33/PWM3 Select 0 : R33 1 : PWM3 R34/PWM4 Select 0 : R34 1 : PWM4 R35/PWM5 Select 0 : R35 1 : PWM5 R3]/Buzzer Select 0 : R36 1 : Buzzer output R37/TMR1 Select 0 : R37 1 : TMR1
MSB
Figure 14-7 PWM Control Register 1
R/W
R/W -
R/W -
R/W -
R/W -
R/W
R/W
R/W LSB
PWMCR2
MSB
-
PO L8 PO L14 C N TB
ADDRESS: 00EBH INITIAL VALUE: 0000 0000 b 14Bit/8Bit PWM Count stop/start 0 : Count start 1 : Count stop 14Bit PWM Output Polarity 0 : Positive Polarity 1 : Negitive Polarity 8Bit PWM Output Polarity 0 : Positive Polarity 1 : Negative Polarity
Figure 14-8 PWM Control Register 2
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15. Interrupt Interval Measurement Circuit
The Interrupt interval measurement circuit is shown in Figure 15-1. The Interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, Edge detector, 8bit counter, measured result storing register, FIFO (9 bit, 6 level) interrupt, Control register, etc. The more details about registers are shown Figure 15-2 .
Data Bus 7 4
IDCR [F9H]
FCLR
IMS
I34H
I34L
ISEL
IDCK
IDST
IDFS [FAH]
DPOL
FOE
FFUL FEMP
PS8 PS9
1 MUX 0 1 MUX Edge detector Clear 8bit counter Overflow 8 4 INT34
INT3
0 MUX 1
0
FCLR FIFO (9bit, 6level)
IDR [FBH]
D7
D6
D5
D4
D3
D2
D1
D0
Figure 15-1 Block Diagram of Interrupt interval measurement circuit
Control The HMS81C4x60 contains a Interrupt interval measurement module. 1. Select interrupt input pin what you want to measure by set the FUNC [00CEH]. 2. Set IDCR [00F9H] : FIFO clear, interrupt mode select, interrupt edge select, external interrupt INT3 select, sampling clock select, COUNT start/stop select. 3. Set IDCR [00F9H] : set IDST to start measuring. 4. Counter value is stored to IDR [00FBH] when selected edge is detected. After data was written, timer is cleard automatically and it counts continue.
5. You can select interrupt occuring point by set Interrupt
Mode Select bit (IMS), every edge what you selected or FIFO 4 level is filled. 6. If input signal's interval is larger than maximum counter value (0FFH), counter occurring an interrupt and count again from 00H. 7. See Figure 15-7 FIFO operating mechanism.
[Example] ;Set INT3 for remote control pulse reception LDM LDM : : FUNC,#0000_1001b;INT3 SET IDCR,#1001_0001b ;64uSec PCS
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R/W
R/W IM S
R/W I34H
R/W I34L
R/W -
R/W ISEL
R/W ID C K
R/W ID ST LSB
IDCR
FC LR MSB
ADDRESS: 00F9H INITIAL VALUE: 0001 -000b Counter control 0 : Stop 1 : Clear & Count Sample Clock Select 0 : PS9(128uSec) 1 : PS8(64uSec) External Interrupt Select 0 : INT3 fixed External Interrupt Edge Select 00 : No Select 01 : Falling Edge 10 : Rising Edge 11 : Both Edge Interrupt Mode 0 : Every Selected Edge by I34H/L 1 : Every FIFO 4Level is Filled FIFO Clear 0 : Ignored 1 : Clear & Return to 0
Figure 15-2 Int. interval determination control register
R/W
R/W
R/W
R/W
R/W
R/W FO E
R/W FF UL
R/W F EM P LSB
IDFS
D PO L MSB
ADDRESS: 00FAH INITIAL VALUE: 0--- -001b FIFO Empty Flag 0 : Data Filled 1 : Empty FIFO Full flag 0 : Not Full 1 : Full FIFO Overrun Error Flag 0 : No Error 1 : Error Detected Data Polarity 0 : Data is stored every falling edge 1 : Data is stored every rising edge
Figure 15-3 Port function select register
W
W -
W EC 3S
W EC 2S
W
W
W
W LSB
FUNC
MSB
-
IN T3S IN T2S IN T1S
ADDRESS: 00CEH INITIAL VALUE: --00 000-b R24/INT3 Select 0 : R23 1 : INT3
Figure 15-4 Port function select register
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Interrupt input
c e f
IDR
d
MSB
R D7
R D6
R D5
R D4
ADDRESS: 00FBH INITIAL VALUE: Undefined R R R R D3 D2 D1 D0 LSB
Figure 15-6 INT. interval determination FIFO data register Item Symbol I34H 1 0 1 1 I34L 0 1 1 1
Frame Cycle
Pulse width
? @ A B
Detecting edge Rising edge Falling edge Both edge Both edge
Figure 15-5 Setting for measurement
1) FIFO storing mechanism FEMP=1, FFUL=0 FEMP=0, FFUL=0 Data 1 FEMP=0, FFUL=0 Data 1 Data 2 FEMP=0, FFUL=1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data in 2) FIFO reading mechanism Read out FEMP=0 Data 1 Data 2 Data in Data in FEMP=0, FFUL=1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 7 Data in Data 6 will be erased. FOE=1 (Over run error) FEMP=0 FEMP=1
Read out
Data 2
Figure 15-7 Example for FIFO operating mechanism
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16. Buzzer driver
The Buzzer driver circuit is shown in Figure 16-1. The Buzzer driver circuit consists of the 6bit counter, 6bit comparator, Buzzer data register BUR(00EEH). The BUR Data Bus 8
BUR [EEH]
BUCK BUCK 1 0 BU5 BU4 BU3 BU2 BU1 BU0
register controls source clock and output frequency. The more details about registers are shown Figure 16-2 .
BUR write
6 6bit Comparator clear PS7 PS8 PS9 PS10 MUX PWMCR1 TM R1 BUZ
EN5 EN4 EN3 EN2 EN1 EN0
Output Generator
BUZZ
00 01 10 11
6 6bit counter clear
Figure 16-1 Block Diagram of Buzzer driver circuit
Control The HMS81C4x60 contains a Buzzer driver module. 1. Select an input clock among PS7~PS10 by set the BUCK1~0 of BUR.
BUCK1 0 0 1 1 BUCK0 0 1 0 1 Clock source PS7 PS8 PS9 PS10
3. Set BUZ bit for output enable. 4. Output waveform is rectagle clock which has 50% duty. 5. You can use this clock for the other purposes.
Buzzer data Register
W W W W W
ADDRESS : 0EEH RESET VALUE : ???? ????b
W W W
BUR
BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0
Input select Buzzer count data ADDRESS : 0EAH RESET VALUE : 0000 0000b
RW RW RW RW RW
PWM control Register 1
RW RW RW
2. Select output frequency by change the BU5~0. Output frequency = 1 / (PSx x BUy x 2) Hz. x=7~10, y=5~0 See example Table 16-1.
Note: Do not select 00H to BU5~0. It means counter stop.
PWMCR1 TM R1 BUZ
EN5
EN4
EN3
EN2
EN1
EN0
R36/Buzz select 0: R36 1: Buzz output
Figure 16-2 Buzzer driver Registers
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BUR5~0 Dec
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Output frequency (KHz) PS7
(32S)
Hex
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
PS8
(64S)
PS9
(128S)
PS10
(256S)
31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496
62.50 31.25 20.872 15.626 12.50 10.416 8.928 8.814 6.942 6.25 5.682 5.208 4.808 4.484 4.166 3.906 3.676 3.472 3.288 3.124 2.876 2.840 2.718 2.604 2.50 2.404 2.316 2.232 2.156 2.084 2.016 1.952 1.894 1.838 1.786 1.736 1.690 1.644 1.602 1.562 1.524 1.488 1.454 1.420 1.388 1.358 1.33 1.302 1.276 1.25 1.226 1.202 1.18 1.158 1.136 1.116 1.096 1.078 1.06 1.042 1.024 1.008 0.992
125.0 62.5 41.744 31.252 25.0 20.832 17.858 17.628 13.884 12.5 12.364 10.416 9.616 8.968 8.332 7.812 7.342 6.944 6.576 6.248 5.752 5.680 5.436 5.208 5.0 4.808 4.632 4.464 4.302 4.168 4.032 3.904 3.788 3.676 3.552 3.472 3.380 3.288 3.204 3.124 3.048 2.978 2.908 2.840 2.776 2.706 2.66 2.604 2.542 2.5 2.452 2.404 2.36 2.316 2.272 2.232 2.192 2.156 2.12 2.084 2.048 2.016 1.984
250.0 125.0 83.488 62.504 50.0 41.664 35.716 35.256 27.768 25.0 24.728 20.832 19.232 17.936 16.664 15.624 14.684 13.888 13.152 12.496 11.504 11.360 10.872 10.416 10.0 9.616 9.262 8.928 8.604 8.336 8.064 7.808 7.576 7.352 7.104 6.944 6.760 6.576 6.408 6.248 6.096 5.956 5.816 5.680 5.552 5.412 5.320 5.208 5.184 5.0 4.904 4.808 4.720 4.632 4.544 4.464 4.384 4.312 4.24 4.168 4.096 4.032 3.968
Table 16-1 . Example for fex=4MHz
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17. On Screen Display (OSD)
The HMS81C4x60 can support 512 OSD chacters and font size is used 12x10, 12x12, 12x14, 12x16, 16x18. It can support 48 character columns and 2 line buffers respectively and also support full screen OSD when use interrupt. Each characters have bit plane of 24bit and support attribute with OSD line and full screen OSD respectively. OSD circuit consists of the Position attribute register, Line register, Full screen screen control register, I/O polarity register, font ROM, VRAM, etc. On Screen Display block diagram is shown in Figure 17-1 and the more details about display characters are shown in Figure 17-2.
Line 1,2 Attribute, Position register L1ATTR [AF0H] L1VPOS [AF1H] L2ATTR [AF3H] L2VPOS [AF4H]
Line register OSDLN [AE5H]
Full screen control register OSDCON1 [AE0H]
Display On/Off Control register OSDCON2 [AE1H] Field detection register FDWSET [AE3H] Edge color register EDGECOL [AE4H]
I/O Porarity Rigister OSDCON3 [AE2H]
Horizontal position register LHPOS [AE6H]
OSD Control Circuit
Color Pallet
DAC
R G B
VRAM
Font ROM
OSD Generation Circuit
Output Control Circuit
YS
dot clock
YM
HSYNC VSYNC
Synchronization Circuit
Xin
PLL
Figure 17-1 Block Diagram of On Screen Display circuit
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[12 x 10 Character Font]
[12 x 12 Character Font] - italic (only 12 x 12 mode can be supported)
[12 x 14 Character Font] Foreground Character - 512 color (8 pallet) - color selecting : VRAM n-character bit 19~16 Background - 512 color (8 pallet) - color selecting : VRAM n-character bit 23~20 Foreground Character outline - setting by LnATTR register - color selecting : EDGECOL register
[12 x 16 Character Font] Character shadow - setting by LnATTR register and VRAM n-character bit 9 - color selecting : EDGECOL register Background shadow color - setting by VRAM n-character bit 15~12 - color selecting : EDGECOL register - 512 color (8 pallet)
[16 x 18 Character Font] OSD background shadow - Character flash - background underline
Figure 17-2 OSD Character Font Example
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17.1 Feature of OSD
The Feature of OSD shown in below. - Font pixel matrix : 12x10, 12x12, 12x14, 12x16, 16x18 dots - The number of font pattern : 512 fonts - Display ability : 48Character x n lines (multilined by OSD interrupt) - 8 foreground pallet of 512 colors for each character - 8 background pallet of 512 colors for each character - Full screen 8 background color - Character size : 3 fonts(2 times, 1.5 times, 1 times) - Progressive scan line switch - Attribute : Outline, Shadow, Rounding - RGB DAC : 8 level each color - Display clock frequency : 12MHz ~ 64MHz
17.2 OSD Registers
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W LSB
OSDCON1
FSBC 3 FSBC 2 FSBC 1 FSBC 0 PR SC N DLIN E D D CLK STO CK
ADDRESS: 0AE0H INITIAL VALUE: 0000 0000b Stop OSD clock 0 :Release OSD clock 1 : Stop OSD clock Double dot clock mode 0 : Normal 1 : Double Double scan line mode 0 : Normal 1 : Double Progressive scan line mode 0 : Interace mode 1 : Progressive mode Full screen background color register 0000 : Transparency 0001 : Half blank 0010 : white 0011 : Black 0111 ~ 0100 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7
MSB
Figure 17-3 OSD Control Registers - 1
OSDCON1 bit 0: STOCK It stop or start OSD clock. If oscillation is stoped, IC's power consumption is decreased. bit 1: DDCLK
If you set this bit to 1, OSD input clock is divided by two , than it makes OSD horisontal image size as doubled. bit 2: DLINE If you set this bit to 1, OSD vertical scan counter input clock is doubled from normal state. It makes OSD vertical
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image size as doubled. bit 3: PRSCN It control progressive scan line mode. bit clear than interace mode and bit set than processive mode.
bit 7~4: FSBC3 ~ FSBC0 It controls full screen background color as figure shows.
NOTE:
Data slicer operate when OSDCON1.PRSCN(0AE0.3) bit of OSD register is cleared. Namely, it operate interace scan display mode.
R/W
R/W
R/W FS 3
R/W FS 2
R/W FS 1
R/W FS 0
R/W
R/W LSB
OSDCON2
FLAR T O BG W
O LN O SD O N
ADDRESS: 0AE1H INITIAL VALUE: 0000 0000b On/off of all OSD 0 :Off 1 : On On OSD line1 and line2 0 : Off OSD line 1 : On OSD line Font size 0000 : 12 x 16 0001 : 12 x 14 0010 : 12 x 12 0011 : 12 x 10 0111 ~ 0100 : Reseved 1000 : 16 x 18 1111 ~ 1001 : Reserved 12/14 dot background width of 1 OSD character 0 : 12 dot 1 : 14 dot Flash rate when closed caption decoder is used 0 : 32 Vsync is one period 1 : 64 Vsync is one period
MSB
Figure 17-4 OSD Control Register - 2
OSDCON2 bit 0: OSDON It controls OSD, Full screen background at once. It does not affect anything to Vsync interrupt and OSD interrupt, etc. bit 1: ONL It controls OSD line1 and line2 on/off. If its value is 1, OSD line is on. bit 2 ~ 5: FS0 ~ FS3
It controls OSD font size. bit 6: OBGW It controls dot background width. Default width is 12dots. If its value is set, 2 dots (background color) are added both left and right side of character. bit 7: FLRAT It controls OSD flash rate when closed caption decoder is used. Bit clear than 32 Vsync is one period and bit set than 64 Vsync is one period.
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W
W
W
W
W
W
W
W LSB
OSDCON3
SELCK1 SELCK2 ONDAC POLRG POLYM POLYS
POLHS POLVS
ADDRESS: 0AE2H INITIAL VALUE: 0000 0000b Vsync polarity 0 : Active low 1 : Active high Hsync polarity 0 : Active low 1 : Active high YS polarity 0 : Active low 1 : Active high YM polarity 0 : Active low 1 : Active high RGB pin polarity 0 : Active low 1 : Active high On/Off of RGB DAC 0 : Off 1 : On Select dot clock 00 : Clock from DLL 01 : Clock from LC OSC for EVA only 10 : Clock 1 for test 11 : Reserved
MSB
Figure 17-5 I/O Polarity(Initial) Register
OSDCON3 bit7~0 : SELCK1, SELCK0, ONDAC, POLRG, POLYM, POLYS, POLHS, POLVS
It controls Hsync/Vsync polarity, YS/YM polarity, RGB polarity, RGB DAC on/off and select dot clock.
W
W
W
W
W
W
W
W LSB
FDWSET
FM AX3 FM AX2 FM AX1 FM AX0 D BFLG F M IN2 FM IN 1 FM IN 0 MSB
ADDRESS: 0AE3H INITIAL VALUE: 0111 1010b Field Detection Min. Pointer Field Detection Polarity 0 : Masking between Min. and Max. 1 : Detect between Min. and Max. Field Detection Max. Pointer
Field Detection Window: ( {1'b0, (FMIN2 ~ FMIN0)} < hptr[10:7] < (FMAX3 ~ FMAX0))
FDWSET FDWSET (Field Detection Window Setting) register detects the begin of Vsync(Vertical Sync.) signal and distinguishs its current field is Even field or Odd field. The region of FMIN[2:0] ~ FMAX[3:0] is field detection
window. FMAX[3:0] can divide the region between Hsync(Horizontal Sync.) by 16 windows. You can assume there is 4 bit horizontal counter, for example HCOUNT[3:0](hptr[10 :7]) which count 0~15.
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HMS81C4x60
If the start of Vsync is detected at the window, next field is even. Else if Vsync is detected another region of the window, next field is odd.
Ex1: VSync(Odd)
Ex2: VSync(Even)
It means start of Vsync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 0, it distinguish odd field. And, start of Vsync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 1, it distinguish even field.
FMAX
FMIN HSync
FMIN[2:0], FMAX[3:0] are compared with the horizontal counter in OSD block.
Figure 17-6 FDWSET detection region
R/W R/W R/W R/W R/W R/W R/W R/W LSB Edge 1 color of shadow, outline, edge 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Edge 2 color of shadow, outline, edge 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7
EDGECOL
EDG2C3 EDG2C2 EDG2C1 EDG2C0 EDG1C3 EDG1C2 EDG1C1 EDG1C0
ADDRESS: 0AE4H INITIAL VALUE: 1000 0111b
MSB
Figure 17-7 Character, Window color Register
EDGECOL bit 7 ~ bit 0 : EDG1C0,EDG1C1,EDG1C2,EDG1C3 EDG2C0,EDG2C1,EDG2C2,EDG2C3
It control shadow color, outline color and edge color. Low 4 bits controls edge 1 shadow, outline color and high 4 bits controls edge 2 shadow, outline color.
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W
W
W
W
W
W
W
W LSB
CHEDCL
W IN C 3 W IN C 2 W IN C 1 W IN C 0 SHEC 3 S HEC 2 SH EC 1 SH EC 0 MSB
ADDRESS: 0AE5H INITIAL VALUE: Undefined Foreground shadow, outline edge color 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Scroll window background color 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7
Figure 17-8 Scroll window color Register
CHEDCL bit 7 ~ bit 0 : SHEC0,SHEC1,SHEC2,SHEC3 WINC0,WINC1,WINC2,WINC3 It controls foreground shadow and outline edge color and
R R R R VLR 4 R VLR 3 R VLR 2
scroll window background color. Low 4 bits controls scroll window background color and high 4 bits controls foreground shadow outline edge color.
R V LR 1
R VLR 0 LSB
OSDLN
MSB
-
ADDRESS: 0AE6H INITIAL VALUE: ---0 0000H OSD line being displayed 00000 : Not displayed any OSD line yet after Vsync 00001 : 1st line OSD being displayed ....... ....... 11111 : 31st line OSD being displayed
Figure 17-9 OSD Line Register
OSDLN bit 4 ~ bit 0 : VLR4 ~ VLR0 It shows current display OSD line from 1 to 31.
MSB OSD Line Horizontal Position 00H~ FFH
LHPOS
W LH7 W LH6 W LH5 W LH4
ADDRESS: 0AE7H INITIAL VALUE: Undefined W W W W LH3 LH2 LH 1 LH 0 LSB
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Figure 17-10 OSD Line Horizontal Position Register
It control OSD line horizontal position. Position value from 00h to FFh.
LHPOS bit 7 ~ bit 0 : LH7 ~ LH0
W W W W W W W W LSB 1 : OSD test mode 1 : Dll test mode 1 : Reset clock count test mode Dot clock frequency R R R R R R R R LSB
DLLMOD
D C KF4 D C KF3 D C KF2 D C KF1 D C KF0 MSB
ADDRESS: 0AE8H INITIAL VALUE: 0000 0000H
DLLTST
MSB
-
ADDRESS: 0AE9H INITIAL VALUE: --00 0000H
Figure 17-11 DLL mode Register
DLLMOD bit 2 ~ 0 : If you set this bit to 1, the status is changed test mode. bit 7 ~ bit 3 : DCKF4 ~ DCKF0 It control dot clock frequency. Dot clock frequency is as below.
Value
DCKF4 DCKF4 DCKF4 DCKF4 DCKF4 DCKF4 DCKF4
Value
DCKF4 DCKF4 DCKF4
Frequency 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 21.33MHz 19.69MHz 18.29MHz 17.07MHz 16.00MHz 15.05MHz 14.22MHz 13.47MHz 12.80MHz 12.19MHz 11.63MHz 11.13MHz 10.67MHz reserved reserved
0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
Frequency 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 stop dll clock reserved reserved 64.00MHz 51.20MHz 42.67MHz 36.57MHz 32.00MHz 28.44MHz 25.60MHz 23.27MHz
1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1 0 0 0
Table 17-1 Dot Clock Frequency (fex=4Mhz)
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W
W
W
W
W
W
W
W L1V8 LSB
L1ATTR
O BG H1 W DS L1 EN O L1 ENSH 1 C SZ11 C SZ10 FSC 1 MSB
ADDRESS: 0AEAH INITIAL VALUE: 0000 0000H OSD line 1 vertical position (bit 8) Foreground shadow or outline color select 0 : Edge 1 color 1 : Edge 2 color Size of character 00 : Normal 01 : 1.5 times 10 : 2 times 11 : Reserved Enable/disable of shadow 0 : Disable 1 : Enable Enable/disable of outline 0 : Disable 1 : Enable Width of shadow, outline 0 : 1 dot 1 : Proportional to character size OSD chraracter background height 0 : font height 1 : font height + 2
Figure 17-12 OSD line 1 attribute register
L1ATTR bit 0 : L1V8 It is equivalent to L1VPOS's most significant bit(bit 8). See more details in L1VPOS. bit 1: FSC1 It selects character outline and shadow color. If it is 1, it select EDGE2 color of EDGECOL register. Or not, it select EDGE1 color. According to EDGECOL register and this bit character and shadow colors are selected simulteneously bit 3~2: CSZ11~CSZ10 It controls OSD character's size ( normal, 1.5 times, 2 times). You can use this register and DDCLK, DLINE bit, horizontal / vertical size can be controlled (x1, x1.5, x2).
bit 4: ENSH1 It enables line 1's character(foreground) shadow. bit 5: ENOL1 It enables line 1's character(foreground) outline. bit 6: WDSL1 It shows thickness of line 1's shadow and outline.This bit is set than one dot and bit clear is proportional to character size. If only character size is 2 times, 2 times per vertically and horizontally. In case 1 dot width would be enable. bit 7: OBGH1 It controls character's background height. Default height is 16dots. If its value is set, 2 dots (background color) are added both top and bottom side of character.
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W
W -
W -
W
W
W
W
W LSB
L1EATR
MSB
-
SEL1U LSEL1O W SEL1FL SEL1IT S EL1SH
ADDRESS: 0AEBH INITIAL VALUE: Undefined Select shadow/round of line 1 each character when VRAM.ENRND is set. 0 : round character 1 : shadow character Select italic/upper edge of line 1 each character. Italic character can be displayed only when character size is 1, 1.5 times, and VRAM.BSU is set. 0 : Upper edge character 1 : Italic character Select flash/left edge of line 1 character when VRAM.BSL is set. 0 : Left edge character 1 : Flash Select OSD/window when display. If this bit is 0, background window would be displayed. 0 : Background window selected 1 : OSD line selected Select underline /lower edge of line 1 each character 0 : Underline 1 : Lower edge line
L1EATR It shows OSD line 1 extend attribute register.
L1ATTR.
L2EATR L1VPOS
W LIV7 MSB OSD line 1 vertical position 000H~ 1FFH W LIV6 W LIV5 W LIV4 ADDRESS: 0AECH INITIAL VALUE: Undefined W W W W LIV3 LIV2 LIV1 LIV0 LSB W MSB W W W
ADDRESS: 0AEEH INITIAL VALUE: Undefined W W W W LSB
SEL2ULSEL2O W SEL2F L SEL2IT SEL2SH
L2EATR It shows OSD line 2's extened attribute register.
L1VPOS It shows OSD line 1's vertical position in 9bit format (LIV8 + L1VPOS, 000 ~ 1FFH).
L2VPOS
W L2V7 W L2V6 W L2V5 W L2V4
ADDRESS: 0AEFH INITIAL VALUE: Undefined W W W W L2V3 L2V2 L2V1 L2V0 LSB
L2ATTR
W MSB W W W
ADDRESS: 0AEDH INITIAL VALUE: Undefined W W W W L2V2 LSB
MSB
O BG H 2 W D SL2 EN O L2 EN SH 2 C SZ 22 C SZ 21 F SC 2
L2VPOS It shows OSD line 2's vertical position. Its function is the same as L1VPOS.
L2ATTR It shows OSD line 2's attributes. Its function is the same as
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WINSH
W MSB W W W
ADDRESS: 0AF0H INITIAL VALUE: Undefined W W W W LSB
VCNT
R MSB R R R
ADDRESS: 0AF4H INITIAL VALUE: Undefined R R R R LSB
W INSH7 W INSH6 W INSH5 W INSH4 W INSH3 W INSH2 W INSH1 W INSH0
VC N T6 VC N T6 VC N T6 VC N T6 VC N T6 VC N T6 VCN T 6 F LD ID Current scan line line vertical position [6:0] Current display field 0 : Odd field 1 : Even field
OSD scroll window start horizontal position
WINSH It shows OSD scroll window start horizontal position. VCNT
It shows Vsync count register and counted by pixel clock.
WINSY
W MSB OSD scroll window start vertical position W W W ADDRESS: 0AF1H INITIAL VALUE: Undefined W W W W LSB
VCNT counter clock start at Vsync start edge.
W INSY7 W INSY6 W INSY5 W INSY4 W INSY3 W INSY2 W INSY1 W INSY0
HCNT
R R R R
ADDRESS: 0AF5H INITIAL VALUE: Undefined R R R R LSB
H C NT 7 H C NT 6 H C NT 5 H C NT 4 H CN T 3 H CN T 2 H C N T1 H C N T0
WINSY It shows OSD scroll window start vertical position.
MSB Horizontal counter hptr[10:3]
HCNT
WINEH
W MSB OSD scroll window end horizontal position W W W ADDRESS: 0AF2H INITIAL VALUE: Undefined W W W W LSB
It shows Hsync count register and counted by pixel clock. HCNT counter clock start at Hsync start edge.
W INEH7 W INEH6 W INEH5 W INEH4 W INEH3 W INEH2 W INEH1 W INEH0
CULTAD
WINEH It shows OSD scroll window end horizontal position.
MSB
W -
W -
W -
W -
ADDRESS: 0AF9H INITIAL VALUE: Undefined W W W W F IL15 LSB
Normal/Test mode select 00 : Normal mode 01 ~ 11 : Test mode
WINEY
W MSB W W W
ADDRESS: 0AF3H INITIAL VALUE: Undefined W W W W LSB
1.5 times character mode 0 : line double mode 1.5 times 1 : field interleaving mode 1.5 times
W INEY7 W INEY6 W INEY5 W INEY4 W INEY3 W INEY2 W INEY1 W INEY0
OSD scroll window end vertical position
CULTAD It shows normal and test mode and 1.5 times mode.
WINEY It shows OSD scroll window end vertical position.
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17.3 VRAM
VRAM contains a OSD line buffer, 48 character's attributes. Each character's attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, character and character number ( 000H ~ 1FFH, 512 characters ), etc.
Line No. Character add. No. 1 2 3 1 : 46 47 48 1 2 3 2 : 46 47 48 Address (bit 47~0) Hexa decimal A80 A81 A82 : AAD AAE AAF B80 B81 B82 : BAD BAE BAF A40 A41 A42 : A6D A6E A6F B40 B41 B42 : B6D B6E B6F A00 A01 A02 : A2D A2E A2F B00 B01 B02 : B2D B2E B2F 0E BSL 0D BSD 0C BSU Bit No. Name Function Edge color of lower and right background shadow edge 0 : edge 1 color 1 : edge 2 color Background shadow upper eddge control/italic depend on LxEATR.SELxIT 0 : disable 1 : enable if(LxEATR.SELxIT == 0) background shadow upper edge enable else(LxEATR.SELxIT == 1) italic enable Background shadow lower edge control/underline depend on LxEATR.SELxUL 0 : disable 1 : enable if(LxEATR.SELxUL == 0) background shadow lower edge enable else(LxEATR.SELxUL == 1)underline enable Background shadoww left edge control/flash(blInking) depend on LxEATR.SELxFL 0 : disable 1 : enable if(LxEATR.SELxFL == 0) background shadow left edge enable else(LxEATR.SELxFL == 1) flash(flicking) enable Background shadow right edge control 0 : disable 1 : enable Foreground color for character (11 colors) Background color for character (12 colors)
0B
BSCDR
Table 17-2 VRAM memory map
0F Bit No. 00~08 Name CG8 ~CG0 ENRND Function 10~13 Character font code 1FFh ~ 000h Round enable/disable 0 : disable 1 : enable Edge color of upper and left background shadow edge 0 : edge 1 color 1 : edge 2 color 14~17
BSR
FC3 ~FC0 BC3 ~BC0
09
Table 17-3 VRAM attribute
0A
BSCUL
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Composition of VRAM
RESET VALUE: Undefined
LINE 1 (page A)
0A80 0A81 0A82 : 0AAF 0B80 0B81 0B82 : 0BAF
CG6 CG5
0A40 0A41 0A42 : 0A6F 0B40 0B41 0B42 : 0B6F
CG4
0A00 Character 1 Attr. 0A01 Character 2 Attr. 0A02 Character 3 Attr. : 0A2F Character 48 Attr. 0B00 0B01 0B02 : 0B2F
CG3 CG2
LINE 2 (page B)
Character 1 Attr. Character 2 Attr. Character 3 Attr. Character 48 Attr.
CG1 CG 0 Character font address (512 fonts)
CG 8
CG7
BSR
BSL
BSD
BSU BSC D R B SCU L EN R N D CG 8 see table 17-3 VRAM attribute
BC 3
BC 2
BC 1
BC 0
FC 3
FC 2
FC1
FC 0 Character color select (11 characters) 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7 Background color select (12 characters) 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7
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17.4 Character ROM
The HMS81C4x60 Character ROM are used 512 types of Font Dot Pattern data. As displayed one character, need 12 x 10 ~ 16 x 18bits Dot Pattern data. 1. Each horizontal data (12dots) needs 2bytes ROM. 2. One character is constructed with 16 horizontal data to vertically. As a result, one character needs 32bytes (2 x 16 bytes). 3. HMS81C4x60 contains 512 characters. Total Font ROM memory size is calculated as 16,384bytes ( 32bytes / character x 512 characters ) 4. Font ROM memory is located from 10000H ~ 17FFFH, this memory can not be accessed by user program.
Charact er code 000H 001H 002H : xyzH : 1FDH 1FEH 1FFH Address range Upper 8bit 14000H ~ 14011H 14020H ~ 14031H 14040H ~ 14051H : (14000H + xyz0H) ~ (14000H + 2*xyzFH) : 17FA0H ~ 17FB1H 17FC0H ~ 17FD1H 17FE0H ~ 17FF1H Lower 8bit 10000H ~ 10011H 10020H ~ 10031H 10040H ~ 10051H : (10000H + xyz0H) ~ (10000H + 2*xyzFH) : 13FA0H ~ 13FD1H 13FC0H ~ 13FD1H 13FE0H ~ 13FF1H Figure 17-13 Character Dot Pattern 16 x 18 12 x 14
5. A character's address and dot position in font ROM is described in Figure 17-13.
Left address
14060 14061 14062 14063 14064 14065 14066 14067 14068 14069 1406A 1406B 1406C 1406D 1406E 1406F 14070 14071 14072 14073 14074 14075 14076 14077 14078 14079 1407A 1407B 1407C 1407D 1407E 1407F
Right address
10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 1006A 1006B 1006C 1006D 1006E 1006F 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 1007A 1007B 1007C 1007D 1007E 1007F
Table 17-4 Font ROM memory map
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17.5 Color Look Up Table
[Example] Color data table
RESET VALUE : Undefined
W 7 W 6 R60 W 5 R50 W 4 R40 W 3 R30 W 2 R20 W 1 R10 W 0 R00
RED0 <0AD0H> RED1 <0AD1H> RED2 <0AD2H> GREEN0 <0AD3H> GREEN1 <0AD4H> GREEN2 <0AD5H> BLUE0 <0AD6H> BLUE1 <0AD7H> BLUE2 <0AD8H>
R07
R71
R62
R51
R41
R31
R21
R11
R01
R72
R62
R52
R42
R32
R22
R12
R02
G70
G60
G50
G40
G30
G20
G10
G00
Color_example_table: db 0000_0000b ;color db 0000_0011b ;color db 0010_1011b ;color ; db 0000_0000b ;color db 0000_0101b ;color db 0100_1101b ;color ; db 0000_0000b ;color db 1001_0001b ;color db 1111_0001b
0 = Gray 1 = Red 2 = Green 3 = Yellow 4 = Blue 5 = Magenta 6 = Cyan 7 = half blue
G71
G61
G51
G41
G31
G21
G11
G01
G72
G62
G52
G42
G32
G22
G12
G02
B70
B60
B50
B40
B30
B20
B10
B00
B71
B61
B51
B41
B31
B21
B11
B01
B72
B62
B52
B42
B32
B22
B12
B02
Composition of color 7 Composition of color 6 Composition of color 5 Composition of color 4
Composition of color 0 Composition of color 1 Composition of color 2 Composition of color 3 Red : {R02,R01,R00} Green : {G02,G01,G00} Blue : {B02,B01,B00}
Figure 17-14 Color look up table
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18. DATA SLICER
HMS81C4x60 supports Closed Caption decoding standard with 0.5MHz data rate. Also it can capture 4 horizontal lines information per frame, because it has 4 horozontal lines capture memory. It is able to select even or odd field at one field interval. Data Slicer captures caption information from line 21 in vertical blanking interval of CVBS, and stores these data to buffer memory.
18.1 Data Slicer Circuit
Figure 18-1 shown the data slicer circuit. CVBS signal is entered to CVBS pin via 0.47uF capacitor. The black level of signal is about 2V. SCAP pin is connected to external 560pF capacitor which adjust the referance voltage of comparator. Its slicer level is adapted to input signal.
SCAP
560pF
CVBS
0.47uF
HMS81C4x60
Figure 18-1 Data Slicer Circuit
18.2 Configuration of Data Slicer
Figure 18-2 shows the block diagram of the Data Slicer.
Run-in key timing Sync-tip timing
Timing Controller Data capture timing
CPU control
CVBS Data Filter Reference Voltage Memory Interface Controller Slicer Memory
Figure 18-2 Data Slicer Block Diagram
This data slicer block separates caption information from CVBS signal. Data slicer composes high speed comparator and on-chip low pass filter. The output data of comparator
is stored in memory through the filter and memory interface controller, which should be decoded to caption data by software. Slicer memory addressed 600h ~ 6FFh.
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18.3 Slicer Registers
Slicer Control Register Slicer Control Register is the specific control register,
R/W R/W R/W R/W R/W R/W R/W
which select operating frequency of the slicer, slicer decoding method and switch slicer on/off.
R/W LSB
SLCON
MSB
-
R IKTST SELC K
D EM E1 D EM E0 S LO N
ADDRESS: 0BE0H INITIAL VALUE: 0000 0000b Slicer On/Off 0 : Slicer Off 1 : Slicer On Decoding Method 00 : Normal 01 : Reserved 10 : Reserved 11 : Reversed Slicer Clock 0 : Normal clock 1 : Test clock RIK slicer test mode 00 : Normal clock 01 : Reserved 10 : Reserved 11 : Reserved
Figure 18-3 Slicer Control Register
Slicer Information Register 0 Slicer Information Register 0 selects even or odd field
W W W W W W W LFC 0
buffer of line 0 and slicer line 0 position. Also it is used to select line number in Vertical blanking interval.
W LF C0 LSB
SLINF0
MSB
SLP O S 0
ADDRESS: 0BE1H INITIAL VALUE: 0000 0000b Line0 enable 00 : disable all line 0 01 : reserved 10 : reserved 11 : enable all line 0 (even and odd field) Slicer line 0 position
Figure 18-4 Slicer Information Register 0
Slicer Information Register 1 Slicer Information Register 1 selects even or odd field
W W W W W W W LFC 1
buffer of line 1 and slicer line 1 position. Also it is used to select line number in Vertical blanking interval.
W LF C1 LSB
SLINF1
MSB
SLP O S 1
ADDRESS: 0BE2H INITIAL VALUE: 0000 0000b Line 1 Field 00 : disable all line 1 01 : reserved 10 : reserved 11 : enable all line 1 (even and odd field) Slicer line 1 position
Figure 18-5 Slicer Information Register 1
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Run-in key Start/End position Register RIKST points the start postion of run-in key, it is delayed from start edge of Hsync. RIKED points the end position of run-in key, it is also delayed from start edge of Hsync.
W W W W W W W
Both timmings are counted up by 8MHz clock. The referance voltage of comparator is charged by external signal during this time interval. Figure 18-6 and Figure 18-7 shows the RIK register's configure.
W LSB
RIKST
R IKST7 R IKST6 R IKST5 R IKST4 R IKST3 R IKST2 R IKST1 RIKST 0 MSB
ADDRESS: 0BE3H INITIAL VALUE: XXXX XXXXb Run-in key window start position
Figure 18-6 Run-in key Start Position Register
W
W
W
W
W
W
W
W LSB
RIKED
R IKED 7 R IKED 6 R IKED 5 R IKED 4 R IKED 3 R IKED 2 RIKED 1 R IKE D0 MSB
ADDRESS: 0BE4H INITIAL VALUE: XXXX XXXXb Run-in key window end position
Figure 18-7 Run-in key End Position Register
Sync Start/End Position Register Sync Start and End position Register are used to make Sync tip window. Both timmings are counted up by
W W W W W W W
16MHz clock. Figure 18-8 and Figure 18-9 shows the Sync-tip register's configure.
W LSB
SNCST
SNCST7 SNCST6 SNCST5 SNCST4 SNCST3 SNCST2 SNCST1 SNCST0 MSB
ADDRESS: 0BE7H INITIAL VALUE: XXXX XXXXb Sync-tip window start position
Figure 18-8 Sync-tip start position register
W
W
W
W
W
W
W
W LSB
SNCED
SNCED7 SNCED6 SNCED5 SNCED4 SNCED3 SNCED2 SNCED1 SNCED0 MSB
ADDRESS: 0BE8H INITIAL VALUE: XXXX XXXXb Sync-tip window end position
Figure 18-9 Sync-tip end position register
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18.4 Data Sampling
Line 21 Closed Caption signal Figure 18-10 shows the closed caption signal. The signal composes color burst, clock run-in, start bit(001), 16bit ASCII data with 2 parity bit. Sliced raw datas are sampled by 4MHz frequency. Interrupt occurrence The slicer interrupt is occured after writing the sliced two lines data to memory buffer. Signal timing Figure 18-11 shows an example of variable signals, which includes Vsync(vertical Sync.), Hsync(horizontal Sync.), CVBS(composit video in), SCAP(slicer capacitor), Run-in key and Sync tip. Line 21 closed caption signal run after Vsync interrupt. The signal's black(base) level voltage is charged on Sync-tip switch-on period, and the referance voltage of comparator is charged on RIK switch-on perid. Because RIK time is related to SCAP voltage(comparator referance voltage or slicer level) which is charged by clock run-in signal, user can adjust the slicer level by RIK time. The sliced data is stored to RAM buffer. (0600h~ 06FFh)
CLOCK RU N IN program color burst
12.91us
[ CAPTION DATA ] TW O (7 BIT + PARITY ) CHARACTERS ( DATA )
START BIT(001)
3.972us 51.26us 61.342us
33.76us
Figure 18-10 Closed caption signal
Address assign Table 18-1 shows the map of assigned buffer memory.
Setting Even Field First Line Odd Field Even Field Secont Line Odd Field 06C0h ~ 06FFh 0640h ~ 067Fh 0680h ~ 06BFh Address 0600h ~ 063Fh
Table 18-1 Address assign
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5V
Vsync
1 5V
2
1 Hsync cycle
5V
Hsync
5V
CVBS
line 21 signal
2.5V 2V
SCAP
Slicer capacitor charging level
2.2V 0.5V
5V
RIK
3
Run-in key start/stop timming
0V 5V
Sync_tip
4
Sync-tip start/stop timming
0V
Figure 18-11 Signal timing
[Example] Initializing slicer register.
CCD_INIT: LDM LDM LDM LDM LDM LDM LDM SLINF0,#0011_0011b SLINF1,#0000_0000b RIKST,#01 RIKED,#8Ch SNCST,#01 SNCED,#58h SLCON,#01h ; ; ; ; ; ; ; slicer line 21 no field run-in key start : 1 -> 0.125uS(8MHz) run-in key end : 8ch -> 17.5uS(8MHz) sync tip start : 1 -> 0.0625uS(16MHz) sync tip end : 58h -> 5.5uS(16MHz) normal clock, 16MHz, slicer start
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19. I2C Bus Interface
The I2C Bus interface circuit is shown in Figure 19-1. The multi-master I2C Bus interface is a serial communications circuit, conforming to the Phlips I2C Bus data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. This multi-master I2C Bus interface circuit consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. The more details about registers are shown Figure 19-2~ Figure 19-5.
ICAR [D8H]
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb
Address comparator
Interrupt Generation Circuit
IFI2CR
ICDR [D9H] SDA Data Control Circuit Noise Elimination Circuit
D7
D6
D5
D4
D3
D2
D1
D0
BB Circuit
ICSR [00DAH]
MST
TRX
BB
PIN
AL
AD0
ADRb
LRB
AL Circuit ICCR [00DBH] SCL Clock Control Circuit Noise Elimination Circuit Clock Source Clock division
B SEL1 B SEL1 ACKb ESO CCR3 CCR2 CCR1 CCR0
Figure 19-1 Block Diagram of multi-master I2C circuit
Control The HMS81C4x60 contains two I2C Bus interface modules. It supports multi-master function, so it contains arbitration lost detection, synchronization function,etc.
ITEM Format Function Philips I2C standard 7bit addressing format Master transmitter Master receiver Slave transmitter Slave receiver
I2C address register It contains slave address (7bit) which is used during slave mode and Read/Write bit. Bit 7 ~ 1 : Slave address 6~0
Note: Bit 7~1 (SAD6~0) store slave address. The address data transmitted from the master is compared with the contents of these bits.
Communication mode
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The more details about its bits are shown Table 19-1.
ADDRESS : 00D8H RESET VALUE : 0000 0000b
RW RW RW RW RW RW RW R
Bit No.
Name
Function 00: Slave / Receiver mode 01: Slave / Transmitter mode 10: Master / Receiver mode 11: Master / Transmitter mode MST is cleared when - After reset. - After the arbitration lost is occured and 1 byte data transmission is finished. - After stop condition is detected. - When start condition is disabled by start condition duplication preventation function. TRX is cleared when - After reset. - When arbitration lost or stop condition is occured . - When MST is `0', and start condition or ACK non-return mode is detected. BB(Bus busy)bit is 1 during bus is busy. This bit can be written by S/W. its value is `1' by start condition, and cleared by stop condition. PIN(Pending Interrupt Not)bit is interrupt request bit. If I2C interrupt request is issued, its value is 0. PIN is cleared when - After 1 byte trasmission / receive is finished. PIN is set when - After reset. - After write instruction is excuted into I2C data shift register ICDR. - When PIN bit low, the output of SCL is pulled down, So if you want to release SCL, you must perform write instruction CDR. Arbitration lost detection flag. If arbitration lost is detected, AL=1, or 0. General call detection flag. If general call is detected, AD0=1, or not 0. * General call : If received address is all `0' . it is called general call. Address represent flag 0 : current contents is address 1 : current contents is data
ICAR
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb
Slave address
Read/Write Bit
Figure 19-2 I2C address Register
I2C data shift register [ICDR] The I2C data shift register is an 8bit shift register to store received data and write transmit data. When transmit data is written into this register, it is transfered to the outside from bit7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I 2 C control register (address 00DCH) is "1". The bit counter is reset by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
ADDRESS : 00D9H RESET VALUE : 0000 0000b
RW RW D6 RW D5 RW D4 RW D3 RW D2 RW D1 RW D0
7 6
MST TRX
5
BB
ICDR
D7
4
PIN
S hift left 1-bit ea ch S C L
Figure 19-3 Data shift register
I2C status register The I2C status register controls the I2C Bus interface status. The low-order 4bits are read only bits and the high-order 4bits can be read out and written to.
3 AL
2
AD0
1
ADRb
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Bit No. 0
Name
Function Last received bit. it is used for receive confirmation. If ACK is returned, LRB=0, or not 1. Table 19-1 Bit function Bit No. Name Function
LRB
7 6
I2C connection control. 00: No connection BSEL1 BSEL0 01: SCL0, SDA0 10: SCL1, SDA1 11: SCL0, SDA0, SCL1, SDA1 ACK If acknowlege clock is returned, this bit is 0, or not 1. I2C Bus interface use enable flag 0: Disabled 1: Enabled SCL Frequency selection SCL frequency = fex / (12 * CCR) Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 fex = 4MHz Not allowed Not allowed 333.3KHz 222.2KHz 166.6KHz 133.3KHz 111.1KHz 95.2KHz 83.3KHz 74.1KHz 66.6KHz 60.6KHz 55.5KHz 51.3KHz 47.6KHz 44.4KHz
ADDRESS : 00DAH RESET VALUE : 0001 0000b
RW RW TRX RW BB RW PIN R AL R AD0 R ADRb R LRB
5
ICSR
MST
4 Figure 19-4 I2C status Register
ESO
I2C control register It controls communication data format. It controls SCL mode, SCL frequency, etc. It contains 8bit data to transmit to external device when trasmitter mode, or received 8bit data from external device when receive mode.
3 2 1 0 CCR3 CCR2 CCR1 CCR0
ADDRESS : 00DBH RESET VALUE : 0000 0000b
RW RW RW RW ESO RW RW RW RW
ICCR
BSEL1 BSEL0 ACKb
CCR3 CCR2 CCR1 CCR0
Figure 19-5 I2C control Register
Table 19-2 Bit function
SCL
PIN
I2C Request
Figure 19-6 Interrupt request signal generation timing
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START condition generation When the ESO bit of the I2C control register (00DBH) is "1", writing to the I2C status register will generate START condition. Refer to Figure 19-7 for the START condition generation timing diagram.
STOP condition generation Writing `C0h' to ICSR will generate a stop condition, when ESO (ICCR bit3) is `1'
ICSR write signal (I2C status reg.) SCL ICSR write signal (I2C status reg.) SDA SCL tSETUP tHOLD BB (Bus busy) flag SDA tBB BB (Bus busy) flag tSETUP : Setup time tHOLD : Hold time tBB : Set time for BB tBB
tSETUP
tHOLD
tSETUP : Setup time tHOLD : Hold time tBB : Set time for BB
Figure 19-8 STOP condition generating timing diagram
Figure 19-7 START condition generation timing
START / STOP condition generation time is shown Table 19-3.
ITEM Timing SPEC. 3.3uS (n=20cycles) 3.3uS (n=20cycles) 3.0uS (n=18cycles)
RESTART condition generation RESTART condition's setting sequence is as followings. 1. Write 020H to I2C status register (ICSR, 00DAH)
Setup time ( tSETUP ) Hold time ( tHOLD ) Set/Reset time for BB flag ( tBB )
2. Write slave address to I2C data shift register (ICDR, 00D9H) 3. Write 0F0H to I2C status register (ICSR, 00DAH)
Table 19-3 Example time ( fex=4MHz )
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START / STOP condition detect START / STOP condition is detected when Table 19-3 is satisfied.
Figure 19-9 START / STOP condition detection timing
START / STOP detection time is showed Table 19-4.
ITEM SCL release time Timing SPEC. > 2.0uS (n=12cycles) > 1.0uS (n=6cycles) > 1.0uS (n=6cycles)
SCL release time
Setup time
SCL tSETUP tHOLD
Hold time
SDA (START)
Table 19-4 Example time ( fex=4MHz )
SDA (STOP)
Address data communication The first transmitted data from master is compared with I2C address register (ICAR, 00D8H). At this time R/W is not compared but it determines next data operation. i.e, transmitting or receiving data
tSETUP : Setup time tHOLD : Hold time
Master -> Slave (with 7bit address)
START Slave addr. ACK 7bit R/W ("0")
Data
ACK
Data
ACK STOP /ACK
Slave -> Master (with 7bit address) Data block from master to slave Data block from slave to master
START Slave addr. ACK 7bit R/W ("1") Data ACK Data ACK STOP
Figure 19-10 Address data communication format
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20. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
6-bit up-counter Clock source (BIT overflow : IFBIT) clear comparator IFWDT Watchdog Timer interrupt
WDT
6-bit compare data enable WDTON[bit5]
to reset CPU
6
WDTCL[bit6] WDTR[bit5~0]
WDTR
[00D7H] Watchdog Timer Register [00D6H]
CKCTLR
Clock control Register
Figure 20-1 Block Diagram of Watchdog Timer
Watchdog Timer Control Figure 20-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary counters unless the binary counter are cleared. At this time, when WDTON=1 a reset is generated, which drives the RESET pin low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (IFWDT) is generated.
CKCTLR ADDRESS : 00D6H RESET VALUE : 0000 0000b
W WDT ON W W W W R ENP BTCL BTS2 BTS1 BTS0 CK
Watchdog timer On/Off control 0: Normal 6bit timer, Watchdog off 1: Watchdog timer ADDRESS : 00D7H RESET VALUE : -011 1111b
W W W W W W ~ W 0
WDTR
WDT CL
W DTR5
Slave address Watchdog timer Clear 0: Watchdog timer free run 1: Watchdog timer clear and free run Automatically cleared this bit after 1cycle
Figure 20-2 Watchdog timer register
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Example: Sets the watchdog timer detection time
LDM LDM Within WDT detection time LDM : : : : LDM : : : : LDM WDTR,#01??????b CKCTLR,#00111???b WDTR,#01??????b ;Clear Counter and set value(??????b) ;You have to set WDTR first, for prevent unpredictable interrupt ;when you set WDTON bit. ;Select clock source(???b) and WDTON=1 ;Clear counter
Within WDT detection time
WDTR,#01??????b
;Clear counter
WDTR,#01??????b
;Clear counter
Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON (bit 5 in CKTCLR) to "1". WDTON is initialized to "0" during reset, WDTON should be set to "1" to operate after reset is released. Example: Enables watchdog timer reset
: LDM : : CKTCLR,#001?????b ;WDTON1
Example: 6-bit timer interrupt setting up.
LDX TXSP LDM LDM : : #03FH ;SP 3F CKTCLR,#000?????b ;WDTON0 WDTR,#01??????b ;WDTCL0
Refer table and see BIT timer ().
CKCTLR BTS2~0 000b 001b BIT input clock PS4 (4uS) PS5 (8uS) PS6 (16uS) PS7 (32uS) PS8 (64uS) PS9 (128uS) PS10 (256uS) PS11 (512uS) Watchdog timer input clock 1,024uS 2,028uS 4,096uS 8,192uS 16,384uS 32,768uS 65,536uS 131,072uS
The watchdog timer is disabled by clearing bit 5 (WDTON) of CKTCLR.
IFWDT cycle 32,256uS 64,512uS 129,024uS 258,048uS 516,096uS 1,032,192uS 2,064,384uS 4,128,768uS
Watchdog Timer Interrupt The watchdog timer can also be used as a simple 6-bit timer by clearing bit 5 (WDTON) of CKTCLR. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below.
T = WDTR x Interval of BIT
010b 011b 100b 101b 110b 111b
The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source.
Table 20-1 Watchdog timer MAX. cycle (Ex:fex=4MHz)
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Source clock BIT overflow
Binary-counter
1
2
3
0
1
2
3
0 Counter Clear
WDTR IFWDT interrupt
n
3 Match Detect
WDTR "0100_0011b" WDT reset reset
Figure 20-3 Watchdog timer Timing
Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. See Figure 20-4.
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INPUT PIN internal pull-up
VDD
VDD
OUTPUT PIN ON OPEN ON OFF
VDD
O
i GND VDD
OFF
O
i GND VDD ON OFF
X
Weak pull-up current flows
OPEN
X
O
O
In the left case, much current flows from port to GND.
VDD INPUT PIN OUTPUT PIN VDD i=0 OPEN i L VDD L OFF i GND Very weak current flows ON i=0 GND
O
ON OFF
X
i=0
GND
X
O
O
When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.
In the left case, Tr. base current flows from port to GND. To avoid power consumption, low output to the port .
Figure 20-4 Application example of Port under Power Consumption
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21. OSCILLATOR CIRCUIT
The HMS81C4x60 has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and OSC1 and OSC2 are input and output for OSD(On Screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 21-1 .
Recommend C1 XOUT fc (MHz) 4 C2 fc (MHz) XIN VSS C1 & C2 (pF) 15
Crystal Oscillator
Open
XOUT
External Clock
XIN
External Oscillator Figure 21-1 Oscillation Circuit
Oscillation components have their own characteristics, so user should consult the component manufacturers for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XOUT XIN
Figure 21-2 Layout example of Oscillator PCB circuit
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22. RESET
The HMS81C4x60 have two types of reset generation procedures; one is an external reset input, other is a watch-dog
On-chip Hardware Program counter RAM page register G-flag of PSW PC DPGR G Initial Value (FFFFH) - (FFFEH) 00H 0
timer reset. Table 22-1 shows on-chip hardware initialization by reset action.
On-chip Hardware Peripheral clock Watchdog timer Control registers Initial Value Off Disable Refer to Table 8-1 on page 22
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connecting for simple power-on-reset is shown in Figure 22-1 .
VDD
RESET + - GND MCU
Figure 22-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
~ ~
Oscillator (XIN pin) RESET Fetch
ADDRESS BUS DATA BUS
~ ~ ~ ~
FFFE FFFF Start
~ ~
?
?
?
?
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST = 62.5mS at 4.19MHz
Figure 22-2 Timing Diagram after RESET
~ ~
RESET Process Step 1 fMAIN /1024 MAIN PROGRAM tST = x 256
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22.2 Watchdog Timer Reset
Refer to "20. WATCHDOG TIMER" on page 90.
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23. OTP Programming
23.1 HMS87C4x60 OTP Programming
User can burn out HMS87C4x60 OTP through the general Gang programmer using special ROM writer. In Devleopment tool package auxiliary, HMS87C4x60 has ROM writer socket. HMS87C4x60 have two ROM memory areas. One is Program ROM memory and the other is Font ROM memory. Program ROM area is from 1000h to FFFFh Font ROM area is from 10000h to 17FFFh. Blank Check Program Writing There are two kind of OTP file. One is program OTP file(***.OTP) and the other is font OTP file(***.FNT). You can make each file through ASMLINKER.exe and OSDFONT.exe respectively. All OTP file is Motolora Sformat. You can burn the program file and font file respectively or together. To burn program file and font file respectively, refer following procedure 1. Make program OTP file and font OTP file repectively.
1000H
2. Burn program OTP file(Set chip target address 1000h ~ FFFFh)
Program Memory
3. Burn font OTP file(Set chip target address 10000h ~17FFFh) To burn program file and font file together, refer following procedure
FFFFH OSD Font Memory 17FFFH
1. Add program OTP file and font OTP file 2. Burn OTP file(Set chip target address 1000h ~ 17FFFh) About other details, refer ROM wirter manual.
Figure 23-1 HMS87C4x60 OTP Memory Map
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23.2 .Device Configuration Data
OM1 OM2 OM3 PGMB
DIO<4>
DIO<0> DIO<1> DIO<2> DIO<3> OEB CEB AHB
ALB 32SDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
DIO<6> DIO<5>
Figure 23-2 Figure Pin Configuration in OTP Programming Mode
HYNIX HMS87C4260
VPP A16
DIO<7>
HMS87C4x60 Mode Program Verify Optional Verify Gang Write Gang Verify VPP 11.25 11.25 5 11.25 11.25, 5 CEB Low Low Low Low Low OEB High Low Low High Low PGMB Low High X Low X
Figure 23-3 Figure Mode Table
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24. Assemble mnemonics
24.1 Instruction Map
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
000 001 010
NOP CLRC CLRG
SET1
dp.bit
BBS
A.bit,rel
BBS
dp.bit,rel
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
TCALL SETA1
0 .bit
BIT
dp
POP
A
PUSH
A
BRK BRA
rel
//
//
//
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1 COM
2 .bit dp
POP
X
PUSH
X
//
//
//
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL NOT1
4 M.bit
TST
dp
POP
Y
PUSH PCALL
Y Upage
011
DI
//
//
//
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1 OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET INC
X
100
CLRV
//
//
//
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1 CMPY CBNE 8 dp dp+X AND1B TCALL EOR1 DBNE 10 dp EOR1B TCALL
12
TXSP
101
SETC
//
//
//
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
//
//
//
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
LDC LDCB STC
M.bit
LDX
dp
LDX
dp+Y
XCN
DAS
111
EI
//
//
//
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STX
dp
STX
dp+Y
XAS
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
000 001 010 011 100 101 110 111
BPL
rel
CLR1
dp.bit
BBC
A.bit,rel
BBC
dp.bit,rel
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
BVC
rel
//
//
//
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL CALL
3 !abs
TEST SUBW
!abs dp
LDY
#imm
JMP
[dp]
BCC
rel
//
//
//
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
TCLR1 CMPW CMPX
!abs dp #imm
CALL
[dp]
BNE
rel
//
//
//
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL DBNE CMPX LDYA CMPY
7 Y !abs dp #imm
RETI TAY TYA DAA NOP
BMI
rel
//
//
//
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV XMA
{X}
CMPY INCW
!abs dp
INC
Y
BVS
rel
//
//
//
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
dp
DECW
dp
DEC
Y
BCS
rel
//
//
//
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY XYX
BEQ
rel
//
//
//
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
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24.2 Alphabetic order table of instruction
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} ADDW dp AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} AND1 M.bit AND1B M.bit ASL A ASL dp ASL dp + X ASL !abs BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BIT dp BIT !abs BMI rel BNE rel BPL rel BRA rel BRK OP CODE 04 05 06 07 15 16 17 14 1D 84 85 86 87 95 96 97 94 8B 8B 08 09 19 18 y2 y3 x2 x3 50 D0 F0 0C 1C 90 70 10 2F 0F BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 2 3 3 2 2 1 3 3 1 2 2 3 2 3 2 3 2 2 2 2 3 2 2 2 2 1 CYCLE NO 2 3 4 4 5 6 6 3 5 2 3 4 4 5 6 6 3 4 4 2 4 5 5 4/6 5/7 4/6 5/7 2/4 2/4 2/4 4 5 2/4 2/4 2/4 4 8 Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Arithmetic shift left -------C -------C N-----Z16-bits add without carry : YA YA + (dp+1)(dp) Logical AND A A ^ (M) NV - - H - ZC NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Bit test A with memory : Z A ^ M, N (M7), V (M6) Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PCL), SP S - 1, M(SP) PSW, SP SP - 1, PCL (0FFDEH), PCH (0FFDFH)
--------------MM - - - - Z --------------MM - - - - Z -----------------------------
---1-0--
38 39 40 41 42 43 44 45 46 47
BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel CLR1 dp.bit CLR1A A.bit CLRC CLRG
30 B0 3B 5F FD 8D y1 2B 20 40
2 2 3 2 3 3 2 2 1 1
2/4 2/4 8 8 5/7 6/8 4 2 2 2
Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel Subroutine call M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0"
---------------
--------
----------------------------0 --0-----
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HMS81C4x60
NO. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
MNENONIC CLRV CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPW dp CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DBNE dp,rel DBNE Y,rel DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DECW dp DI DIV EI EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} EOR1 M.bit EOR1B M.bit INC A INC dp INC dp + X INC !abs INC X INC Y INCW dp JMP !abs JMP [!abs] JMP [dp]
OP CODE 80 44 45 46 47 55 56 57 54 5D 5E 6C 7C 7E 8C 9C 2C DF CF AC 7B A8 A9 B9 B8 AF BE BD 60 9B E0 A4 A5 A6 A7 B5 96 97 94 AB AB 88 89 99 98 8F 9E 9D 1B 1F 3F
BYTE NO. 1 2 2 2 3 3 2 2 1 2 2 2 3 2 2 3 2 1 1 3 2 1 2 2 3 1 1 2 1 1 1 2 2 2 3 3 2 2 1 3 3 1 2 2 3 1 1 2 3 3 2
CYCLE NO 2 2 3 4 4 5 6 6 3 4 2 3 4 2 3 4 4 3 3 5/7 4/6 2 4 5 5 2 2 6 3 12 3 2 3 4 4 5 6 6 3 5 5 2 4 5 5 2 2 6 3 5 4 Clear V-flag : V "0"
OPERATION
FLAG NVGBHIZC -0--0---
Compare accumulator contents with memory contents A - (M)
N - - - - - ZC
Compare YA contents with memory pair contents : YA - (dp+1)(dp) Compare X contents with memory contents X - (M) Compare Y contents with memory contents Y - (M) 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement and branch if not equal : if (M) 0, then PC PC + rel. Decrement MM-1
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC N-----ZN - - - - - ZC N - - - - - ZC --------
N-----Z-
Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Disable interrupts : I "0" Divide : YA / X Q:A, R:Y Enable interrupts : I "1" Exclusive OR A A (M)
N-----Z-----0-NV - - H - Z -----1--
N-----Z-
Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Increment (M) (M) + 1
-------C -------C N - - - - - ZC
N-----Z-
Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 Unconditional jump PC jump address
N-----Z--------
November 2001 Ver 1.1
101
HMS81C4x60
NO. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
MNENONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDC M.bit LDCB M.bit LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs LDYA dp LSR A LSR dp LSR dp + X LSR !abs MUL NOP NOT1 M.bit OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} OR1 M.bit OR1B M.bit PCALL
OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB CB CB E4 1E CC CD DC 3E C9 D9 D8 7D 48 49 59 58 5B 00,FF 4B 64 65 66 67 75 76 77 74 6B 6B 4F
BYTE NO. 2 2 2 3 3 2 2 1 1 3 3 3 2 2 2 3 2 2 2 3 2 1 2 2 3 1 1 3 2 2 2 3 3 2 2 1 3 3 2
CYCLE NO 2 3 4 4 5 6 6 3 4 4 4 5 2 3 4 4 2 3 4 4 5 2 4 5 5 9 2 5 2 3 4 4 5 6 6 3 5 5 6 Load X-register Y (M) Load accumulator A (M)
OPERATION
FLAG NVGBHIZC
N-----Z-
X-register auto-increment : A (M), X X + 1 Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------C -------C --------
N-----Z-
Load YA : YA (dp+1)(dp) Logical shift right
N-----Z-
76543210 C "0"
Multiply : YA Y x A No operation Bit complement : (M.bit) ~(M.bit) Logical OR A A V (M)
N - - - - - ZC
N-----Z---------------
N-----Z-
Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PCL (upage), PCH "OFFH"
-------C -------C --------
138 139 140 141 142 143 144 145 146 147
POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI
0D 2D 4D 6D 0E 2E 4E 6E 6F 7F
1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 5 6
Pop from stack SP SP + 1, Reg. M(SP) -------(restored) Push to stack M(SP) Reg. SP SP - 1 --------
Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP)
--------
(restored)
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HMS81C4x60
NO. 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187
MNENONIC ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X} SET1 dp.bit SETA1 A.bit SETC SETG STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STC M.bit STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs STYA dp SUBW dp TAX TAY TCALL n
OP CODE 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 x1 0B A0 C0 E5 E6 E7 F5 F6 F7 F4 FB EB EC ED FC E9 F9 F8 DD 3D E8 9F nA
BYTE NO. 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 2 1 1 2 2 3 3 2 2 1 1 3 2 2 3 2 2 3 2 2 1 1 1
CYCLE NO 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 4 2 2 2 3 4 4 5 6 6 3 4 6 4 5 5 4 5 5 5 5 2 2 8
OPERATION Rotate left through carry
FLAG NVGBHIZC
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store accumulator contents in memory (M) A
---------------------1 --1-----
--------
X-register auto-increment : (M) A, X X + 1 Store C-flag : (M.bit) C Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp) Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PCL (Table vector L), PCH (Table vector H) ---------------------NV - - H - ZC N-----ZN-----Z---------------
188 189 190 191 192 193 194 195 196
TCLR1 !abs TSET1 !abs TSPX TST dp TXA TXSP TYA XAX XAY
5C 3C AE 4C C8 8E BF EE DE
3 3 1 2 1 1 1 1 1
6 6 2 3 2 2 2 4 4
Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) Transfer stack-pointer contents to X-register : X SP Test memory contents for negative or zero : (dp) - 00H Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA
N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z---------------
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103
HMS81C4x60
NO. 197 198 199 200 201
MNENONIC XCN XMA dp XMA dp + X XMA {X} XYX
OP CODE CE BC AD BB FE
BYTE NO. 1 2 2 1 1
CYCLE NO 5 5 6 5 4 A7 ~ A4 f A3 ~ A0
OPERATION Exchange nibbles within the accumulator: Exchange memory contents with accumulator (M) f A Exchange X-register contents with Y-register : X f Y
FLAG NVGBHIZC N-----Z-
N-----Z--------
24.3 Instruction Table by Function 1. Arithmetic/Logic Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y OP CODE 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1 CYCLE NO 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement MM-1 N-----ZN-----ZN - - - - - ZC N - - - - - ZC Compare Y contents with memory contents Y - (M) N - - - - - ZC Compare X contents with memory contents X - (M) N - - - - - ZC N - - - - - ZC Arithmetic shift left N-----ZLogical AND A A ^ (M) NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Compare accumulator contents with memory contents A - (M)
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HMS81C4x60
NO. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV
MNENONIC
OP CODE 9B A4 A5 A6 A7 B5 96 97 94 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
BYTE NO. 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
CYCLE NO 12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Logical shift right Increment (M) (M) + 1 Exclusive OR A A (M)
OPERATION Divide : YA / X Q:A, R:Y
FLAG NVGBHIZC NV - - H - Z -
EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X} TST dp XCN
N-----Z-
N - - - - - ZC
N-----Z-
76543210 C "0"
Multiply : YA Y x A Logical OR A A V (M)
N - - - - - ZC
N-----Z-
N-----Z-
Rotate left through carry
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
Test memory contents for negative or zero : (dp) - 00H Exchange nibbles within the accumulator: A7 ~ A4 f A3 ~ A0
N-----ZN-----Z-
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HMS81C4x60
2. Register / Memory Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNENONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp + X XMA {X} XYX OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE BYTE NO. 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 CYCLE NO 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 3 4 4 5 6 6 3 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Exchange X-register contents with Y-register : X f Y -------Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X SP Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA Exchange memory contents with accumulator (M) f A N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------Store Y-register contents in memory (M) Y -------X-register auto-increment : (M) A, X X + 1 Store X-register contents in memory (M) X --------------Store accumulator contents in memory (M) A Load X-register Y (M) N-----ZX-register auto-increment : A (M), X X + 1 Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------N-----ZLoad accumulator A (M) OPERATION FLAG NVGBHIZC
3. 16-Bit Operation
NO. 1 2 3 4 MNENONIC ADDW dp CMPW dp DECW dp INCW dp OP CODE 1D 5D BD 9D BYTE NO. 2 2 2 2 CYCLE NO 5 4 6 6 OPERATION 16-bits add without carry : YA YA + (dp+1)(dp) Compare YA contents with memory pair contents : YA - (dp+1)(dp) Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 N-----ZN-----ZFLAG NVGBHIZC NV - - H - ZC N - - - - - ZC
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NO. 5 6 7
MNENONIC LDYA dp STYA dp SUBW dp
OP CODE 7D DD 3D
BYTE NO. 2 2 2
CYCLE NO 5 5 5
OPERATION Load YA : YA (dp+1)(dp) Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp)
FLAG NVGBHIZC N-----Z-------NV - - H - ZC
4. Bit Manipulation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNENONIC AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLR1A A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs OP CODE 8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C BYTE NO. 3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 CYCLE NO 4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 OPERATION Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Bit test A with memory : Z A ^ M, N (M7), V (M6) Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Bit complement : (M.bit) ~(M.bit) Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : (M.bit) C Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) FLAG NVGBHIZC -------C -------C MM - - - - Z ---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
5. Branch / Jump Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 MNENONIC BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel OP CODE y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 BYTE NO. 2 3 2 3 2 2 2 2 2 2 2 2 2 CYCLE NO 4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel OPERATION FLAG NVGBHIZC --------------MM - - - - Z ---------------------------------------------------------
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HMS81C4x60
NO. 14 15 16 17 18 19 20 21 22 23
MNENONIC CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL
OP CODE 3B 5F FD 8D AC 7B 1B 1F 3F 4F
BYTE NO. 3 2 3 3 3 2 3 3 2 2
CYCLE NO 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Subroutine call
OPERATION
FLAG NVGBHIZC --------
M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Decrement and branch if not equal : if (M) 0, then PC PC + rel. Unconditional jump PC jump address U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PCL (upage), PCH "OFFH"
---------------
--------
--------
24
TCALL n
nA
1
8
Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PCL (Table vector L), PCH (Table vector H) --------
6. Control Operation & etc.
NO. 1 MNENONIC BRK OP CODE 0F BYTE NO. 1 CYCLE NO 8 Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PCL), SP S - 1, M(SP) PSW, SP SP - 1, PCL (0FFDEH), PCH (0FFDFH) 2 3 4 5 6 7 8 9 10 11 12 13 14 DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F 7F 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 2 4 4 4 4 4 4 4 4 5 6 Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP) (restored) -------Push to stack M(SP) Reg. SP SP - 1 -------(restored) Disable interrupts : I "0" Enable interrupts : I "1" No operation Pop from stack SP SP + 1, Reg. M(SP) ------------0------1-----------1-0-OPERATION FLAG NVGBHIZC
108
November 2001 Ver 1.1

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